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M69AW048B

set to ‘0000h’, and the data of the fifth cycle is the

Power-Down

Configuration

data

(see

Table

5., Power-Down Configuration Data). If the fourth

cycle is written into a different address, the se-

quence is aborted. In the last cycle, a read is made

from the specific Power-Down Configuration ad-

dress (see Table 6., Power-Down Configuration

Addresses). The Power-Down Configuration data

and address must correspond, otherwise the se-

quence is aborted.

When this sequence is performed to take the de-

vice from one PAR mode to another, the write data

may be lost. So, if a PAR mode is used, this se-

quence should be performed prior to any normal

read or write operations.

Table 2. Operating Modes

1. Should not be kept in this logic condition for a period longer than 1µs.

2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-

tention depend on the selection of Power-Down programming.

a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;

Table 3. Power-Down Modes

Operation

E1

E2

W

G

LB

UB

DQ0-DQ7

DQ8-DQ15

Power

Standby (Deselected)

X

X

X

X

Hi-Z

Hi-Z

X

X

X

X

X

Hi-Z

Hi-Z

Power-Down

Hi-Z

Hi-Z

Output Disable

Data Output

Hi-Z

Data Input

Hi-Z

No Write

Hi-Z

Hi-Z

Output Disable

Hi-Z

Data Output

Hi-Z

Data Input

Data Output

Data Output

(3)

Data Input

Data Input

Mode

Data Retention

Retention Address

Deep Power-Down (Default)

No

N/A

4Mb PAR

4 Mbit

00000h – 3FFFFh

8Mb PAR

8 Mbit

00000h – 7FFFFh

16Mb PAR

16 Mbit

00000h – FFFFFh