| 数据搜索系统,热门电子元器件搜索 |
|
M69AW048B 数据表(PDF) 14 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
M69AW048B 数据表(HTML) 14 Page - STMicroelectronics |
|
14 / 29 page ![]() M69AW048B 14/29 Table 11. Read Mode AC Characteristics Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Address should not be changed within minimum Read Cycle Time. 3. The output load 50pF with 50 Ω termination to VCC*0.5 V. 4. The output load 5pF without any other load. 5. Applicable to A3 to A20 when E1 is kept Low. 6. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access. 7. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4µs. In other words, Page Read Cycle must be closed within 4µs. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied. Symbol Alt. Parameter M69AW048B Unit Min Max tAVAX (1,2) tRC Address Valid Time 70 1000 ns tAVAX2 (1,6,7) tPRC Page Read Cycle Time 25 1000 ns tAVEH2 (1,6,7) tPRC Page Read Cycle Time 25 1000 ns tAVEL tASC Address Valid to Chip Enable Low –5 ns tAVGL tASO Address Valid to Output Enable Low 10 ns tAVQV (3,5) tAA Address Valid to Output Valid 70 ns tAVQV2 (3,6) tPAA Page Address Access Time 18 ns tAXAV (5,8) tAX Address Invalid Time 10 ns tAXAV2 (6,8) tAXP Page Address Invalid Time 10 ns tAXQX (3) tOH Data hold from address change 3 ns tBHQX (3) tOH Upper/Lower Byte Enable High to Output Transition 3 ns tBHQZ (4) tBHZ Upper/Lower Byte Enable High to Output Hi-Z 20 ns tBLQV (3) tBA Upper/Lower Byte Enable Low to Output Valid 30 ns tBLQX (4) tBLZ Upper/Lower Byte Enable Low to Output Transition 0 ns tEHAX (9) tCHAH Chip Enable High to Address Invalid –5 ns tEHEL tCP Chip Enable High to Chip Enable Low 15 ns tEHQX (3) tOH Chip Enable High to Output Transition 3 ns tEHQZ (4) tCHZ Chip Enable High to Output Hi-Z 20 ns tELAX (1,2) tRC Read Cycle Time 70 1000 ns tELEH (1,2) tRC Read Cycle Time 70 1000 ns tELQV (3) tCE Chip Enable Low to Output Valid 70 ns tELQX (4) tCLZ Chip Enable Low to Output Transition 3 ns tGHAX tOHAH Output Enable High to Address Invalid –5 ns tGHQX (3) tOH Output Data Hold Time 3 ns tGHQZ (4) tOHZ Output Enable High to Output Hi-Z 20 ns tGLQV (3) tOE Output Enable Low to Output Valid 40 ns tGLQX (4) tOLZ Output Enable Low to Output Transition 0 ns |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |