M69AW048B datasheet(4/29 Pages) STMICROELECTRONICS

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M69AW048B

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SUMMARY DESCRIPTION

The M69AW048B is a 32 Mbit (33,554,432 bit)

CMOS memory, organized as 2,097,152 words by

16 bits, and is supplied by a single 2.7V to 3.3V

supply voltage range.

M69AW048B is a member of STMicroelectronics

PSRAM memory family. These devices are manu-

factured using dynamic random access memory

cells, to minimize the cell size, and maximize the

amount of memory that can be implemented in a

given area.

However, through the use of internal control logic,

the device is fully static in its operation, requiring

no external clocks or timing strobes, and has a

standard Asynchronous SRAM Interface.

The internal control logic of the M69AW048B han-

dles the periodic refresh cycle, automatically, and

without user involvement.

Write cycles can be performed on a single byte by

using Upper Byte Enable (UB) and Lower Byte En-

able (LB).

The device can be put into standby mode using

Chip Enable (E1) or in Power-Down mode by us-

ing Chip Enable (E2).

The device features various kinds of Power-Down

modes for power saving as a user configurable op-

tion:

■

The Partial Array Refresh (PAR) performs a

limited refresh of the part of the PSRAM array

(4 Mbits, 8 Mbits, 16Mbits) that contains

essential data.

■

Deep Power-Down mode: this mode achieves

a very low current consumption by halting all

the internal activities. Since the refresh

circuitry is halted, the duration of the power-

down should be less than the maximum period

for refresh.

Figure 2. Logic Diagram

Table 1. Signal Names

AI05844c

A0-A20

DQ0-DQ15

VCC

M69AW048B

VSS

A0-A20

Address Input

DQ0-DQ15

Data Input/Output

E1, E2

Chip Enable, Power Down

Output Enable

Write Enable

Upper Byte Enable

Lower Byte Enable

VCC

Supply Voltage

VSS

Ground

Not Connected

(no internal connection)

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