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S29AS008J 数据表(PDF) 49 Page - Cypress Semiconductor |
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S29AS008J 数据表(HTML) 49 Page - Cypress Semiconductor |
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49 / 56 page  Document Number: 002-00870 Rev.*K Page 49 of 56 S29AS008J 18.6 Alternate CE# Controlled Erase/Program Operations Notes 1. Not 100% tested. 2. See Erase and Programming Performance on page 51 for more information. Parameter Speed Options JEDEC Std Description 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 35 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tSR/W Latency Between Read and Write Operations Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 6 µs Word Typ 6 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec |
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