S29AS008J datasheet(27/56 Pages) CYPRESS

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Document Number: 002-00870 Rev.*K

Page 27 of 56

S29AS008J

Figure 10.1 Program Operation

Note

See Table on page 30 for program command sequence.

10.7

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a

set-up command. Two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm

automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not

required to provide any controls or timings during these operations. Table on page 30 shows the address and data requirements for

the chip erase command sequence.

Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware reset during the chip

erase operation immediately terminates the operation. The Chip Erase command sequence should be reinitiated once the device

has returned to reading array data, to ensure data integrity.

The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write Operation Status

on page 34 for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading

array data and addresses are no longer latched.

Figure 10.2 on page 29 illustrates the algorithm for the erase operation. See Erase/Program Operations on page 45 for parameters,

and Figure 18.6 on page 46 for timing diagrams.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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