Document Number: 002-00870 Rev.*K

Page 9 of 56

S29AS008J

7.

Device Bus Operations

This section describes the requirements and use of the device bus operations, which are initiated through the internal command

register. The command register itself does not occupy any addressable memory location. The register is composed of latches that

store the commands, along with the address and data information needed to execute the command. The contents of the register

serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table lists the device bus

operations, the inputs and control levels they require, and the resulting output. The following subsections describe each of these

operations in further detail.

Legend

Notes

2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See Sector Group Protection/Unprotection

on page 15.

7.1

Word/Byte Configuration

The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is

set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.

If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by

CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.

7.2

Requirements for Reading Array Data

whether the device outputs array data in words or bytes.

The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no

spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array

data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the

device data outputs. The device remains enabled for read access until the command register contents are altered.

S29AS008J Device Bus Operations

Operation

CE#

OE# WE#

RESET#

WP#

Addresses

(Note 1)

DQ0–

DQ7

DQ8–DQ15

BYTE#

BYTE#

Read

L

L

H

H

X

DQ8–DQ14 = High-

Z, DQ15 = A-1

Write (Program/

Erase)

LH

L

H

(Note 3

)

Standby

0.2 V

XX

0.2 V

H

X

High-Z

High-Z

High-Z

Output Disable

L

H

H

H

X

X

High-Z

High-Z

High-Z

Reset

X

X

X

L

X

X

High-Z

High-Z

High-Z

Sector Group Protect

(Note 2)

LH

L

X

Sector Address,

A6 = L, A3 = A2 = L,

A1 = H, A0 = L

XX

Sector Group

Unprotect (Note 2)

LH

L

H

Sector Address,

A6 = H, A3 = A2 = L,

A1 = H, A0 = L

XX

Temporary Sector

Group Unprotect

XX

X

High-Z