SLK2721

OC48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

WITH ENHANCED JITTER TOLERANCE

SLLS532 − JUNE 2002

5

POST OFFICE BOX 655303

Terminal Functions (Continued)

control/status pins

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

TYPE

DESCRIPTION

AUTO_DETECT

34

TTL input (with pulldown)

Data rate autodetect enable. Enable the autodetection function for different data rates.

CONFIG0

CONFIG1

17

18

TTL input (with pulldown)

Configuration pins. Put the device under one of the four operation modes: TX only, RX

only, transceiver, or repeater.

ENABLE

44

TTL input (with pullup)

Standby enable. When this pin is held low, the device is disabled for IDDQ testing.

When high, the device operates normally.

FRAME_EN

27

TTL input (with pullup)

Frame sync enable. When this pin is asserted high, the frame synchronization circuit

for byte alignment is turned on.

LCKREFN

24

TTL input (with pullup)

Lock to reference. When this pin is low, RXCLKP/N output is forced to lock to REFCLK.

When high, RXCLKP/N is the divided down clock extracted from the receive serial

data.

LLOOP

53

TTL input (with pulldown)

Local loopback enable. When this pin is high, the serial output is internally looped back

to its serial input.

LOL

45

TTL output

Loss of lock. When the clock recovery loop has locked to the input data stream and the

phase differs by less than 100 ppm from REFCLK, then LOL is high. When the phase of

the input data stream differs by more than 100 ppm from REFCLK, then LOL is low. If

the difference is too large (> 500 ppm), the LOL output is not valid.

LOOPTIME

51

TTL input (with pulldown)

Loop timing mode. When this pin is high, the PLL for the clock synthesizer is bypassed.

The recovered clock timing is used to send the transmit data.

LOS

46

TTL output

Loss of signal. When no transitions appear on the input data stream for more than

2.3

µs, a loss of signal occurs and LOS goes high. The device also transmits all zeroes

downstream using REFCLK as its clock source. When a valid SONET signal is

received, the LOS signal goes low.

PAR_VALID

2

TTL output

Parity checker output. The internal parity checker on the parallel side of the transmitter

checks for even parity. If there is a parity error, the pin is pulsed low for two clock cycles.

PRBSEN

41

TTL input (with pulldown)

PRBS testing enable. When this pin is asserted high, the device is put into the PRBS

testing mode.

PRBSPASS

42

TTL output

PRBS test result. This pin reports the status of the PRBS test results (high = pass).

When PRBSEN is disabled, the PRBSPASS pin is set low. When PRBSEN is enabled

and a valid PRBS is received, then the PRBSPASS pin is set high.

PRE1

PRE2

4

5

TTL input (with pulldown)

Programmable de-emphasis control. Combinations of these two bits can be used to

optimize serial data transmission.

PS

21

TTL input (with pulldown)

Polarity select. This pin, used with the SIGDET pin, sets the polarity of SIGSET. When

high, SIGDET is an active low signal. When low, SIGDET is an active high signal.

RATEOUT0

RATEOUT1

37

36

TTL output

Autorate detection outputs. When AUTO_DETECT is high, the autodetection circuit

generates these two bits to indicate the data rates for the downstream device.

RESET

48

TTL input (with pulldown)

TXFIFO and LOL reset pin. Low is reset and high is normal operation.

RLOOP

54

TTL input (with pulldown)

Remote loopback enable. When this pin is high, the serial input is internally looped

back to its serial output with the timing extracted from the serial data.

RSEL0

RSEL1

39

38

TTL input (with pulldown)

Data rate configuration pins. Put the device under one of the four data rate operations:

OC-48, OC-24, OC-12, or OC-3.

RX_MONITOR

47

TTL input (with pulldown)

RX parallel data monitor in repeater mode. This pin is only used when the device is put

under repeater mode. When high, the RX demultiplexer circuit is enabled and the

parallel data is presented. When low, the demultiplexer is shut down to save power.

SIGDET

20

TTL input (with pulldown)

Signal detect. This pin is generally connected to the output of an optical receiver. This

signal may be active high or active low depending on the optical receiver. The SIGDET

input is XORed with the PS pin to select the active state. When SIGDET is in the

inactive state, data is processed normally. When activated, indicating a loss of signal

event, the transmitter transmits all zeroes and force the LOS signal to go high.