SLK2721

OC48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

WITH ENHANCED JITTER TOLERANCE

SLLS532 − JUNE 2002

9

POST OFFICE BOX 655303

detailed description (continued)

clock and data recovery

The CDR unit of the SLK2721 device recovers the clock and data from the incoming data streams.

In the event of receive data loss, the PLL automatically locks to the local REFCLK to maintain frequency stability.

If the frequency of the data differs by more that 100 ppm with respect to the REFCLK frequency, the LOL pin

is asserted as a warning. Actual loss of lock occurs if the data frequency differs by more than 170 ppm.

minimum transition density

The loop filter transfer function is optimized to enable the CDR to track ppm difference in the clocking and

tolerate the minimum transition density that can be received in a SONET data signal (

±20 ppm). The transfer

function yields a typical capture time of 3500-bit times for random incoming NRZ data after the device is powered

up and achieves frequency locking.

The device tolerates up to 72 consecutive digits (CID) without sustaining an error.

jitter tolerance

Input jitter tolerance is defined as the peak-to-peak amplitude of sinusoidal jitter applied on the input signal that

causes the equivalent 1-dB optical/electrical power penalty. This refers to the ability of the device to withstand

input jitter without causing a recovered data error. The device has a jitter tolerance that exceeds the mask shown

f0

f1

f2

f3

f4

Frequency − Hz

A3

A2

A1

Slope = −20 dB / Decade

Slope = −20 dB / Decade

OC-N/STS-N

LEVEL

f0

(Hz)

F1

(Hz)

F2

(Hz)

F3

(kHz)

F4

(kHz)

A1

(Ulpp)

A2

(Ulpp)

A3

(Ulpp)

3

10

30

300

6.5

65

0.15

1.5

15

12

10

30

300

25

250

0.15

1.5

15

24

Not specified

48

10

600

6000

100

1000

0.15

1.5

15

Figure 2. Input Jitter Tolerance

jitter generation

no jitter is presented to the inputs. The measurement bandwidth for intrinsic jitter is 12 kHz to 20 MHz.

loop timing mode

When LOOPTIME is high, the clock synthesizer used to serialize the transmit data is bypassed and the timing

is provided by the recovered clock. However, REFCLK is still needed for the recovery loop operation.