SLK2721

OC48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

WITH ENHANCED JITTER TOLERANCE

SLLS532 − JUNE 2002

12

POST OFFICE BOX 655303

detailed description (continued)

1:4 Serial to

Parallel

4:1 Parallel to

Serial

RXDATA (3−0)

RXCLK

2.488 GHz

PLL

D

D

SRXDIP

SRXDIN

LLOOP

STXDOP

STXDON

Recovered Clock

Figure 4. Remote Loopback Data Path/Repeater Mode Operation

PRBS

The SLK2721 device has two built-in pseudorandom bit stream (PRBS) functions. The PRBS generator is used

to transmit a PRBS signal. The PRBS verifier is used to check and verify a received PRBS signal.

When the PRBSEN pin is high, the PRBS generator and verifier are both enabled. A PRBS is generated and

fed into the parallel transmitter input bus. Data from the normal input source is ignored in PRBS mode. The

PBRS pattern is then fed through the transmitter circuitry as if it was normal data and sent out by the transmitter.

The output can be sent to a bit error rate tester (BERT) or to the receiver of another SLK2721 device. If an error

occurs in the PRBS pattern, the PRBSPASS pin is set low for two RXCLKP/N cycles.

power-on reset

Upon application of minimum valid power, the SLK2721 device generates a power-on reset. During the

power-on reset the PRXDATA[0:3] signal pins go to 3-state. RXCLKP and RXCLKN are held low. The length

of the power-on reset cycle is dependent upon the REFCLKP and REFCLKN frequency but is less than 1 ms

in duration.