SLK2721

OC48+FEC/24/12/3 SONET/SDH MULTIRATE TRANSCEIVER

WITH ENHANCED JITTER TOLERANCE

SLLS532 − JUNE 2002

15

POST OFFICE BOX 655303

PLL performance specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

PLL startup lock time

VDD, VDDC = 2.375 V, after REFCLK is stable

1

ms

Acquisition lock time

Valid SONET signal or PRBS OC-48

2031

Bit

Times

serial transmitter/receiver characteristics

PARAMETER

TEST CONDITIONS

MIN

NOM

MAX

UNIT

Vodd = |STXDOP−STXDON| transmit

PRE1 = 0,

PRE2 = 0, Rt = 50,

See Table 4 and Figure 1

650

850

1000

mV

Vodd = |STXDOP−STXDON|, transmit

differential output voltage under

PRE1 = 1,

PRE2 = 0

550

750

900

,

differential output voltage under

de-emphasis

PRE1 = 0,

PRE2 = 1

540

700

860

mV

de-emphasis

PRE1 = 1,

PRE2 = 1

500

650

800

mV

V(CMT)

Transmit common mode voltage range

Rt = 50

Ω

1100

1250

1400

mV

Receiver Input voltage requirement,

Vid = |SRXDIP−SRXDIN|

150

mV

V(CMR)

Receiver common mode voltage range

1100

1250

2250

mV

Il

Receiver input leakage

−550

550

µA

Rl

Receiver differential impedance

80

100

120

Ω

CI

Receiver input capacitance

1

pF

td(TX_Latency)

50

Bit

td(RX_Latency)

50

Bit

Times

serial differential switching characteristics over recommended operating conditions (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tt

Differential signal rise time (20% to 80%)

RL = 50 Ω,

80

100

140

ps

tj

Output jitter

Jitter-free data,

12 kHz to 20 MHz, RLOOP = 1

0.05

0.1

UI(pp)

RLOOP = 1

1 MHz

0.15

0.4

Jitter tolerance

RLOOP = 1

See Figure 3

100 kHz

1.5

4

UI(pp)

Jitter tolerance

See Figure 3

1 kHz

1.5

9

UI(pp)