ST6262C datasheet(24/78 Pages) STMICROELECTRONICS

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ST62T52C ST62T62C/E62C

RESETS (Cont’d)

3.2.6 MCU Initialization Sequence

When a reset occurs the stack is reset, the PC is

loaded with the address of the Reset Vector (locat-

ed in program ROM starting at address 0FFEh). A

jump to the beginning of the user program must be

coded at this address. Following a Reset, the In-

terrupt flag is automatically set, so that the CPU is

in Non Maskable Interrupt mode; this prevents the

initialisation routine from being interrupted. The in-

itialisation routine should therefore be terminated

by a RETI instruction, in order to revert to normal

mode and enable interrupts. If no pending interrupt

is present at the end of the initialisation routine, the

MCU will continue by processing the instruction

immediately following the RETI instruction. If, how-

ever, a pending interrupt is present, it will be serv-

iced.

Figure 15. Reset and Interrupt Processing

Figure 16. Reset Block Diagram

RESET

VECTOR

JP:2 BYTES/4 CYCLES

RETI

RETI: 1 BYTE/2 CYCLES

INITIALIZATION

ROUTINE

VA00181

VDD

RESET

RPU

RESD

POWER

WATCHDOG RESET

COUNTER

RESET

ST6

INTERNAL

RESET

fOSC

RESET

ON RESET

LVD RESET

VR02107A

AND. Wired

1) Resistive ESD protection. Value not guaranteed.

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