ST6262C datasheet(49/78 Pages) STMICROELECTRONICS

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ST62T52C ST62T62C/E62C

AUTO-RELOAD TIMER (Cont’d)

AR Status Control Register 1(ARSC1)

Address: D7h

—

Read/Write

Bist 7-5 = PS2-PS0:

Prescaler Division Selection

Bits 2-0. These bits determine the Prescaler divi-

sion ratio. The prescaler itself is not affected by

these bits. The prescaler division ratio is listed in the

following table:

Table 14. Prescaler Division Ratio Selection

Bit 4 = D4:

Reserved. Must be kept reset.

Bit 3-2 = SL1-SL0:

Timer Input Edge Control Bits 1-

0. These bits control the edge function of the Timer

input pin for external synchronization. If bit SL0 is re-

set, edge detection is disabled; if set edge detection

is enabled. If bit SL1 is reset, the AR Timer input pin

is rising edge sensitive; if set, it is falling edge sen-

sitive.

Bit 1-0 = CC1-CC0:

Clock Source Select Bit 1-0.

These bits select the clock source for the AR Timer

through the AR Multiplexer. The programming of

the clock sources is explained in the following Table

15 :

Table 15. Clock Source Selection.

AR Load Register ARLR. The ARLR load register

is used to read or write the ARTC counter register

“on the fly” (while it is counting). The ARLR regis-

ter is not affected by system reset.

AR Load Register (ARLR)

Address: DBh

—

Read/Write

Bit 7-0 = D7-D0:

Load Register Data Bits. These

are the load register data bits.

AR Reload/Capture Register. The ARRC re-

load/capture register is used to hold the auto-re-

load value which is automatically loaded into the

counter when overflow occurs.

AR Reload/Capture (ARRC)

Address: D9h

—

Read/Write

Bit 7-0 = D7-D0:

Reload/Capture Data Bits. These

are the Reload/Capture register data bits.

AR Compare Register. The CP compare register

is used to hold the compare value for the compare

function.

AR Compare Register (ARCP)

Address: DAh

—

Read/Write

Bit 7-0 = D7-D0:

Compare Data Bits. These are

the Compare register data bits.

PS2

PS1

PS0

SL1

SL0

CC1

CC0

PS2

PS1

PS0

ARPSC Division Ratio

128

SL1

SL0

Edge Detection

Disabled

Rising Edge

Falling Edge

CC1

CC0

Clock Source

Fint

Fint Divided by 3

ARTIMin Input Clock

Reserved

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