ST6262C datasheet(42/78 Pages) STMICROELECTRONICS

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ST62T52C ST62T62C/E62C

TIMER (Cont’d)

4.2.1 Timer Operation

The Timer prescaler is clocked by the prescaler

clock input (fINT ÷ 12).

The user can select the desired prescaler division

ratio through the PS2, PS1, PS0 bits. When the

TCR count reaches 0, it sets the TMZ bit in the

TSCR. The TMZ bit can be tested under program

control to perform a timer function whenever it

goes high.

4.2.2 Timer Interrupt

When the counter register decrements to zero with

the ETI (Enable Timer Interrupt) bit set to one, an

interrupt request associated with Interrupt Vector

#4 is generated. When the counter decrements to

zero, the TMZ bit in the TSCR register is set to

one.

4.2.3 Application Notes

TMZ is set when the counter reaches zero; howev-

er, it may also be set by writing 00h in the TCR

The TMZ bit must be cleared by user software

when servicing the timer interrupt to avoid unde-

sired interrupts when leaving the interrupt service

routine. After reset, the 8-bit counter register is

loaded with 0FFh, while the 7-bit prescaler is load-

ed with 07Fh, and the TSCR register is cleared.

This means that the Timer is stopped (PSI=“0”)

and the timer interrupt is disabled.

Figure 26. Timer Working Principle

BIT0

BIT1

BIT2

BIT3

BIT6

BIT5

BIT4

CLOCK

7-BIT PRESCALER

8-1 MULTIPLEXER

8-BIT COUNTER

BIT0

BIT1

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

PS0

PS1

PS2

VA00186

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