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ISL6277HRZ 数据表(PDF) 7 Page - Renesas Technology Corp |
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ISL6277HRZ 数据表(HTML) 7 Page - Renesas Technology Corp |
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7 / 37 page ![]() ISL6277 FN8270 Rev 1.00 Page 7 of 37 Mar 8, 2012 Pin Configuration ISL6277 (48 LD QFN) TOP VIEW 1 48 GND PAD (BOTTOM) 2 3 ISEN2_NB 4 IMON_NB 5 6 SVC 7 PWROK 8 SVD 9 VDDIO 10 SVT 11 VR_HOT_L 12 IMON 47 46 45 44 43 42 41 40 NTC_NB 39 38 37 BOOTX 36 VIN 35 34 BOOT2 33 UGATE2 32 PHASE2 31 LGATE2 30 VDDP 29 VDD 28 PWM_Y 27 LGATE1 26 PHASE1 25 UGATE1 NTC ENABLE Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 1 ISEN2_NB Individual current sensing for Channel 2 of the Northbridge VR. When ISEN2_NB is pulled to +5V, the controller will disable Channel 2 and the Northbridge VR will run single-phase. 2 NTC_NB Thermistor input to VR_HOT_L circuit to monitor Northbridge VR temperature. 3 IMON_NB Northbridge output current monitor. A current proportional to the Northbridge VR output current is sourced from this pin. 4SVC Serial VID clock input from the CPU processor master device. 5 VR_HOT_L Thermal indicator signal to AMD CPU. Thermal overload open drain output indicator active LOW. 6 SVD Serial VID data bi-directional signal from the CPU processor master device to the VR. 7 VDDIO VDDIO is the processor memory interface power rail and this pin serves as the reference to the controller IC for this processor I/O signal level. 8 SVT Serial VID Telemetry (SVT) data line input to the CPU from the controller IC. Telemetry and VID-on-the-fly complete signal provided from this pin. 9 ENABLE Enable input. A high level logic on this pin enables both VRs. 10 PWROK System power good input. When this pin is high, the SVI 2 interface is active and the I2C protocol is running. While this pin is low, the SVC and SVD input states determine the pre-PWROK metal VID. This pin must be low prior to the ISL6277 PGOOD output going high per the AMD SVI 2.0 Controller Guidelines. 11 IMON Core output current monitor. A current proportional to the Core VR output current is sourced from this pin. 12 NTC Thermistor input to VR_HOT_L circuit to monitor Core VR temperature. 13 ISEN3 ISEN3 is the individual current sensing for Channel 3. When ISEN3 is pulled to +5V, the controller disables Channel 3, and the Core VR runs in two-phase mode. 14 ISEN2 Individual current sensing for Channel 2 of the Core VR. When ISEN2 is pulled to +5V, the controller disables Channel 2, and the Core VR runs in single-phase mode. |
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