ISL6277HRZ datasheet(14/37 Pages) RENESAS

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ISL6277

FN8270 Rev 1.00

Page 14 of 37

Mar 8, 2012

Theory of Operation

Multiphase R3™ Modulator

The ISL6277 is a multiphase regulator implementing two voltage

regulators, CORE VR and Northbridge (NB) VR, on one chip

controlled by AMD’s™ SVI2™ protocol. The CORE VR can be

programmed for 1-, 2- or 3-phase operation. The Northbridge VR

can be configured for 1- or 2-phase operation. Both regulators use

the Intersil patented R3™ (Robust Ripple Regulator) modulator.

The R3™ modulator combines the best features of fixed frequency

PWM and hysteretic PWM while eliminating many of their

shortcomings. Figure 7 conceptually shows the multiphase R3™

modulator circuit, and Figure 8 shows the operation principles.

Inside the IC, the modulator uses the master clock circuit to

generate the clocks for the slave circuits. The modulator

discharges the ripple capacitor Crm with a current source equal

to gmVo, where gm is a gain factor. Crm voltage VCRM is a

sawtooth waveform traversing between the VW and COMP

voltages. It resets to VW when it hits COMP, and generates a

one-shot master clock signal. A phase sequencer distributes the

master clock signal to the slave circuits. If the CORE VR is in

3-phase mode, the master clock signal is distributed to the three

phases, and the Clock 1~3 signals will be 120° out-of-phase. If

the Core VR is in 2-phase mode, the master clock signal is

distributed to Phases 1 and 2, and the Clock1 and Clock2 signals

will be 180° out-of-phase. If the Core VR is in 1-phase mode, the

master clock signal will be distributed to Phase 1 only and be the

Clock1 signal.

Each slave circuit has its own ripple capacitor Crs, whose voltage

mimics the inductor ripple current. A gm amplifier converts the

inductor voltage into a current source to charge and discharge

Crs. The slave circuit turns on its PWM pulse upon receiving the

clock signal, and the current source charges Crs. When Crs

voltage VCrs hits VW, the slave circuit turns off the PWM pulse,

and the current source discharges Crs.

Since the controller works with Vcrs, which are large amplitude

and noise-free synthesized signals, it achieves lower phase jitter

than conventional hysteretic mode and fixed PWM mode

controllers. Unlike conventional hysteretic mode converters, the

error amplifier allows the ISL6277 to maintain a 0.5% output

voltage accuracy.

Figure 9 shows the operation principles during load insertion

response. The COMP voltage rises during load insertion,

generating the master clock signal more quickly, so the PWM

pulses turn on earlier, increasing the effective switching

frequency. This allows for higher control loop bandwidth than

conventional fixed frequency PWM controllers. The VW voltage

rises as the COMP voltage rises, making the PWM pulses wider.

During load release response, the COMP voltage falls. It takes

the master clock circuit longer to generate the next master clock

signal so the PWM pulse is held off until needed. The VW voltage

falls as the COMP voltage falls, reducing the current PWM pulse

width. This kind of behavior gives the ISL6277 excellent response

speed.

The fact that all the phases share the same VW window voltage

also ensures excellent dynamic current balance among phases.

FIGURE 7. R3

™ MODULATOR CIRCUIT

CRM

GMVO

MASTER

CLOCK

COMP

MASTER

CLOCK

PHASE

SEQUENCER

CLOCK1

CLOCK2

IL1

CLOCK1

PHASE1

CRS1

PWM1

IL2

CLOCK2

PHASE2

CRS2

PWM2

VCRM

VCRS1

VCRS2

MASTER CLOCK CIRCUIT

SLAVE CIRCUIT 1

SLAVE CIRCUIT 2

IL3

CLOCK3

PHASE3

CRS3

PWM3

VCRS3

SLAVE CIRCUIT 3

CLOCK3

FIGURE 8. R3

™ MODULATOR OPERATION PRINCIPLES IN

STEADY STATE

COMP

VCRM

MASTER

CLOCK

PWM1

CLOCK1

PWM2

CLOCK2

HYSTERETIC

WINDOW

PWM3

VCRS3

CLOCK3

VCRS2

VCRS1

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