ISL6277HRZ datasheet(21/37 Pages) RENESAS

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ISL6277

FN8270 Rev 1.00

Page 21 of 37

Mar 8, 2012

Floating DriverX & PWM_Y Configuration

The ISL6277 allows for one internal driver and one PWM output

to be configured to opposite VRs depending on the desired

configuration of the Northbridge VR. Internal DriverX can be used

as Channel 1 of the Northbridge VR with PWM_Y used for

Channel 3 of the Core VR. Using this partitioning, a 2+1 or 1+1

configured ISL6277 would not require an external driver.

If routing of the driver signals would be a cause of concern due to

having an internal driver on the Northbridge VR, then the

ISL6277 can be configured to use PWM_Y as Channel 1 on the

Northbridge VR. DriverX would then be used as Channel 3 of the

Core VR. This allows the placement of the external drivers for the

Northbridge VR to be closer to the output stage(s) depending on

the number of active Phases, providing placement and layout

flexibility to the Northbridge VR.

VID-on-the-Fly Slew Rate Selection

The FCCM_NB resistor is also used to select the slew rate for VID

changes commanded by the processor. Once selected, the slew

rate is locked in during soft-start and is not adjustable during

operation. The lowest slew rate which can be selected is

10mV/µs which is above the minimum of 7.5mV/µs required by

the SVI2 specification. The slew rate selected sets the slew rate

for both Core and Northbridge VRs; they cannot be independently

selected.

CCM Switching Frequency

The Core and Northbridge VR switching frequency is set by the

programming resistors on COMP_NB and FCCM_NC. When the

ISL6277 is in continuous conduction mode (CCM), the switching

frequency is not absolutely constant due to the nature of the R3™

modulator. As explained in “Multiphase R3™ Modulator” on

page 14, the effective switching frequency increases during load

insertion and decreases during load release to achieve fast

response. Thus, the switching frequency is relatively constant at

steady state. Variation is expected when the power stage

condition, such as input voltage, output voltage, load, etc.

changes. The variation is usually less than 10% and does not

have any significant effect on output voltage ripple magnitude.

Table 5 defines the switching frequency based on the resistor

values used to program the COMP_NB and FCCM_NB pins. Use

the previous tables related to COMP_NB and FCCM_NB to

determine the correct resistor value in these ranges to program

the desired output offset, Slew Rate and DriverX/PWM_Y

configuration.

The controller monitors SVI commands to determine when to

enter power-saving mode, implement dynamic VID changes, and

shut down individual outputs.

AMD Serial VID Interface 2.0

The on-board Serial VID Interface 2.0 (SVI 2) circuitry allows the

AMD processor to directly control the Core and Northbridge

voltage reference levels within the ISL6277. Once the PWROK

signal goes high, the IC begins monitoring the SVC and SVD pins

for instructions. The ISL6277 uses a digital-to-analog converter

(DAC) to generate a reference voltage based on the decoded SVI

value. See Figure 12 for a simple SVI interface timing diagram.

Pre-PWROK Metal VID

Typical motherboard start-up begins with the controller decoding

the SVC and SVD inputs to determine the pre-PWROK Metal VID

setting (see Table 6). Once the ENABLE input exceeds the rising

threshold, the ISL6277 decodes and locks the decoded value into

an on-board hold register.

TABLE 4. FCCM_NB RESISTOR SELECTION

RESISTOR VALUE

[kΩ]

SLEW RATE FOR CORE

AND NORTHBRIDGE

[mV/µs]

DriverX

PWM_Y

5.62

Core VR

Channel 3

NB VR

Channel 1

9.53

13.3

12.5

16.9

21.0

26.7

34.0

12.5

41.2

57.6

NB VR

Channel 1

Core VR

Channel 3

73.2

95.3

12.5

121

154

182

221

12.5

OPEN

TABLE 5. SWITCHING FREQUENCY SELECTION

FREQUENCY

[kHz]

COMP_NB

RANGE [kΩ]

FCCM_NB

RANGE [kΩ]

300

57.6 to OPEN

21.0 to 41.2

154 to OPEN

350

5.62 to 41.2

21.0 to 41.2

154 to OPEN

400

57.6 to OPEN

5.62 to 16.9

57.6 to 121

450

5.62 to 41.2

5.62 to 16.9

57.6 to 121

TABLE 6. PRE-PWROK METAL VID CODES

SVC

SVD

OUTPUT VOLTAGE (V)

1.1

1.0

0.9

0.8

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