ISL6277HRZ datasheet(22/37 Pages) RENESAS

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ISL6277

FN8270 Rev 1.00

Page 22 of 37

Mar 8, 2012

Once the programming pins are read, the internal DAC circuitry

begins to ramp Core and Northbridge VRs to the decoded

pre-PWROK Metal VID output level. The digital soft-start circuitry

ramps the internal reference to the target gradually at a fixed

rate of approximately 5mV/µs until the output voltage reaches

~250mV and then at the programmed slew rate. The controlled

ramp of all output voltage planes reduces in-rush current during

the soft-start interval. At the end of the soft-start interval, the

PGOOD and PGOOD_NB outputs transition high, indicating both

output planes are within regulation limits.

If the ENABLE input falls below the enable falling threshold, the

ISL6277 tri-states both outputs. PGOOD and PGOOD_NB are

pulled low with the loss of ENABLE. The Core and Northbridge VR

output voltages decay, based on output capacitance and load

leakage resistance. If bias to VDD falls below the POR level, the

ISL6277 responds in the manner previously described. Once VDD

and ENABLE rise above their respective rising thresholds, the

internal DAC circuitry re-acquires a pre-PWROK metal VID code,

and the controller soft-starts.

SVI Interface Active

Once the Core and Northbridge VRs have successfully soft-started

and PGOOD and PGOOD_NB signals transition high, PWROK can

be asserted externally to the ISL6277. Once PWROK is asserted

to the IC, SVI instructions can begin as the controller actively

monitors the SVI interface. Details of the SVI Bus protocol are

provided in the “AMD Serial VID Interface 2.0 (SVI2)

Specification”. See AMD publication #48022.

Once a VID change command is received, the ISL6277 decodes

the information to determine which VR is affected and the VID

target is determined by the byte combinations in Table 7. The

internal DAC circuitry steps the output voltage of the VR

commanded to the new VID level. During this time, one or more

of the VR outputs could be targeted. In the event either VR is

commanded to power-off by serial VID commands, the PGOOD

signal remains asserted.

If the PWROK input is de-asserted, then the controller steps both

the Core and the Northbridge VRs back to the stored pre-PWROK

metal VID level in the holding register from initial soft-start. No

attempt is made to read the SVC and SVD inputs during this time.

If PWROK is re-asserted, then the ISL6277 SVI interface waits for

instructions.

If ENABLE goes low during normal operation, all external

MOSFETs are tri-stated and both PGOOD and PGOOD_NB are

pulled low. This event clears the pre-PWROK metal VID code and

forces the controller to check SVC and SVD upon restart, storing

the pre-PWROK metal VID code found on restart.

A POR event on either VCC or VIN during normal operation shuts

down both regulators, and both PGOOD outputs are pulled low.

The pre-PWROK metal VID code is not retained.

VID-on-the-Fly Transition

Once PWROK is high, the ISL6277 detects this flag and begins

monitoring the SVC and SVD pins for SVI instructions. The

microprocessor follows the protocol outlined in the following

sections to send instructions for VID-on-the-fly transitions. The

ISL6277 decodes the instruction and acknowledges the new VID

code. For VID codes higher than the current VID level, the

ISL6277 begins stepping the commanded VR outputs to the new

VID target with the slew rate programmed by the FCCM_NB

resistor.

When the VID codes are lower than the current VID level, the

ISL6277 checks the state of power state bits in the SVI

command. If power state bits are not active, the controller begins

stepping the regulator output to the new VID target. If the power

state bits are active, the controller allows the output voltage to

decay and slowly steps the DAC down with the natural decay of

the output. This allows the controller to quickly recover and move

to a high VID code if commanded.

SVI Data Communication Protocol

The SVI WIRE protocol is based on the I2C bus concept. Two wires

[serial clock (SVC) and serial data (SVD)], carry information

between the AMD processor (master) and VR controller (slave) on

the bus. The master initiates and terminates SVI transactions

and drives the clock, SVC, during a transaction. The AMD

processor is always the master, and the voltage regulators are

the slaves. The slave receives the SVI transactions and acts

accordingly. Mobile SVI WIRE protocol timing is based on

high-speed mode I2C. See AMD publication #48022 for

additional details.

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