ISL62391, ISL62392, ISL62391C, ISL62392C

FN6666 Rev 8.00

Page 13 of 22

August 25, 2015

Theory of Operation

Three Output Controller

The ISL62391, ISL62392, ISL62391C and ISL62392C generate

three regulated output voltages. Two are produced with switch-

mode power supplies (SMPS), and the third by a low dropout

linear regulator (LDO). An additional 5V LDO (PVCC) is used to

power the chip during operation, allowing the ISL62391,

ISL62392, ISL62391C and ISL62392C to regulate all outputs

from a single power source (VIN) with no need for a separate

quiescent supply. This makes the ISL62391, ISL62392,

ISL62391C and ISL62392C an ideal choice as system regulator

for notebook PCs. Because the two SMPS channels are

identical and almost entirely independent, all conclusions drawn

apply to both channels unless otherwise noted.

Modulator and Switching Frequency

The ISL62391, ISL62392, ISL62391C and ISL62392C

frequency PWM and variable frequency hysteretic control.

switching frequency and PWM duty cycle in response to input

representation of the output inductor ripple current. The duty-

provided by a transconductance amplifier that measures the

written as Equation 1:

thresholds. The PWM switching frequency is proportional to

Equation 3 illustrates how to calculate the window size based

on output voltage and frequency set resistor.

The frequency can be expressed in Equation 4:

For Equations 3 through 5:

Power-On Reset

The ISL62391, ISL62392, ISL62391C and ISL62392C are

disabled until the voltage at the VIN pin has increased above

the rising power-on reset (POR) threshold. Conversely, the

controller will be disabled when the voltage at the VIN pin

decreases below the falling POR threshold.

In addition to VIN POR, the PVCC pin is also monitored. If its

voltage falls below 4.2V, the SMPS outputs will be shut down.

This ensures that there is sufficient BOOT voltage to enhance

the upper MOSFET.

EN, Soft-Start and PGOOD

The ISL62391, ISL62392, ISL62391C and ISL62392C use a

digital soft-start circuit to ramp the output voltage of each

SMPS to the programmed regulation setpoint at a predictable

slew rate. The slew rate of the soft-start sequence has been

selected to limit the in-rush current through the output

capacitors as they charge to the desired regulation voltage.

When the EN pins are pulled above their rising thresholds, the

begins to rise. The FB pin ramps to 0.6V in approximately 1.5ms

and the PGOOD pin goes to high impedance approximately

1.25ms after the FB pin voltage reaches 0.6V.

–





=

(EQ. 1)



=

(EQ. 2)

FIGURE 23. MODULATOR WAVEFORMS DURING LOAD

TRANSIENT

PWM

ERROR AMPLIFIER

–

 R

W





=

(EQ. 3)

1



------------------

=

(EQ. 4)

1



---------------------

=

(EQ. 5)