ISL62391, ISL62392, ISL62391C, ISL62392C

FN6666 Rev 8.00

Page 17 of 22

August 25, 2015

Compensation Design

Figure 27 shows the recommended Type-II compensation circuit.

The FB pin is the inverting input of the error amplifier. The COMP

signal, the output of the error amplifier, is inside the chip and

the IC that connects across the FB pin and the COMP signal.

frequency domain transfer function is given by Equation 15:

The LC output filter has a double pole at its resonant frequency

ISL62391, ISL62392, ISL62391C and ISL62392C make the LC

output filter resemble a first order system in which the closed loop

stability can be achieved with the recommended Type-II

compensation network. Intersil provides a PC-based tool

(example page is shown later) that can be used to calculate

compensation network component values and help simulate

the loop frequency response.

3.3V Linear Regulator

In addition to the two SMPS outputs, the ISL62391, ISL62392,

ISL62391C and ISL62392C also provide a fixed 3.3V LDO output

(LDO3) capable of sourcing 100mA continuous current. LDO3

draws its power from PVCC and can be independently enabled

from both SMPS channels.

LDO3 also has a current limit feature with a nominal level of

180mA. Currents in excess of the limit will cause the LDO3

voltage to drop dramatically, limiting the power dissipation.

Thermal Monitor and Protection

LDO3 and PVCC LDOs can dissipate non-trivial power inside the

ISL62391, ISL62392, ISL62391C and ISL62392C at high input-

to-output voltage ratios and full load conditions. To protect the

silicon, ISL62391, ISL62392, ISL62391C and ISL62392C

continually monitor the die temperature. If the temperature

power dissipation. The outputs will remain off until the junction

General Application Design Guide

This design guide is intended to provide a high-level explanation

of the steps necessary to design a single-phase power

converter. It is assumed that the reader is familiar with many of

the basic skills and techniques referenced in the following

section. In addition to this guide, Intersil provides complete

reference designs that include schematics, bills of materials, and

example board layouts.

Selecting the LC Output Filter

The duty cycle of an ideal buck converter is a function of the

input and the output voltage. This relationship is written as

Equation 16:

The output inductor peak-to-peak ripple current is written as

Equation 17:

to 40% of the maximum DC output load current. The value of

switching loss, inductor core loss, and the resistive loss of the

inductor winding. The DC copper loss of the inductor can be

estimated by Equation 18:

The copper loss can be significant so attention has to be given

to the DCR selection. Another factor to consider when

choosing the inductor is its saturation characteristics at

elevated temperature. A saturated inductor could cause

destruction of circuit components, as well as nuisance OCP

faults.

of the voltage drop across the capacitor ESR and of the voltage

change stemming from charge moved in and out of the

capacitor. These two voltages are written as Equation 19:

and Equation 20:

If the output of the converter has to support a load with high

pulsating current, several capacitors will need to be paralleled to

inductance of the capacitor can cause a brief voltage dip if the



TOP

–

-------------------------------------

=

(EQ. 14)

(EQ. 15)



+

 C



FB



+



FB



+









-------------------------------------------------------------------------------------------

=

ISL62391, ISL62392

EA

+

FB

-

REF

VO

FIGURE 27. COMPENSATION REFERENCE CIRCUIT

COMP

D

---------

=

(EQ. 16)

(EQ. 17)

–







------------------------------

=

(EQ. 18)



=

V

ESR



SR

=

(EQ. 19)

V

C



-----------------------------

=

(EQ. 20)