ISL62391, ISL62392, ISL62391C, ISL62392C

FN6666 Rev 8.00

Page 16 of 22

August 25, 2015

Where:

overcurrent setpoint

OCP circuit

- DCR is the inductor DC resistance

sense the inductor current. To sense the inductor current

correctly, not only in DC operation but also during dynamic

needs to match the inductor time constant L/DCR. The value of

For example, if L is 1.5µH, DCR is 4.5m

prevent false OCP during this time, a 10µA current source

flows out of the ISEN1 pin, generating a voltage drop on the

ISEN1 pin current source will be removed.

When an OCP fault is declared, the PGOOD pin will pull-down

to 32

until the EN pin has been pulled below the falling EN threshold

threshold.

When using a discrete current sense resistor, inductor

time-constant matching is not required. Equation 7 remains

unchanged, but Equation 8 is modified in Equation 11:

Furthermore, Equation 9 is changed in Equation 12:

Overvoltage Protection

The OVP fault detection circuit triggers after the FB pin voltage

is above the rising overvoltage threshold for more than 2µs.

The FB pin voltage is 0.6V in normal operation. The rising

overvoltage threshold is typically 116% of that value, or

1.16*0.6V = 0.696V.

For ISL62391, ISL62392, ISL62391C and ISL62392C, when an

OVP fault is declared, the PGOOD pin will pull-down with 32

and latch-off the converter. The OVP fault will remain latched

until the EN pin has been pulled below the falling EN threshold

threshold. During the latch condition, the ISL62391 and

ISL62391C will tri-state the PHASE node by turning both

UGATE and LGATE off until the latch is cleared.

Although latched, the ISL62392 and ISL62392C LGATE gate-

driver output will retain the ability to toggle the low-side

MOSFET on and off in response to the output voltage

transversing the OVP rising and falling thresholds. The LGATE

gate-driver will turn on the low-side MOSFET to discharge the

output voltage, thus protecting the load from potentially

damaging voltage levels. The LGATE gate-driver will turn off the

low-side MOSFET once the FB pin voltage is lower than the

falling overvoltage threshold for more than 2µs. The falling

overvoltage threshold is typically 106% of the reference voltage,

or 1.06*0.6V = 0.636V. This soft-crowbar process repeats as

long as the output voltage fault is present, allowing the ISL62392

and ISL62392C to protect against persistent overvoltage

conditions.

Undervoltage Protection

The UVP fault detection circuit triggers after the FB pin voltage is

below the undervoltage threshold for more than 2µs. The

undervoltage threshold is typically 86% of the reference voltage,

or 0.86*0.6V = 0.516V. If a UVP fault is declared, the PGOOD

pin will pull-down with 32

will remain latched until the EN pin has been pulled below the

POR threshold.

Programming the Output Voltage

When the converter is in regulation, there will be 0.6V between

the FB and GND pins. Connect a two-resistor voltage divider

across the OUT and GND pins with the output node connected

to the FB pin, as shown in Figure 27. Scale the voltage-divider

network such that the FB pin is 0.6V with respect to the GND

pin when the converter is regulating at the desired output

voltage. The output voltage can be programmed from 0.6V to

5.5V.

Programming the output voltage is written as Equation 13:

Where:

- The voltage to which the converter regulates the FB pin is

from the FB pin to the converter output. In addition to

setting the output voltage, this resistor is part of the loop

compensation network

connects from the FB pin to the GND pin

(EQ. 10)

L



-----------------------------------------

=



10

AR

OCSET



–

=

(EQ. 11)



10

A

-------------------------------------

=

(EQ. 12)

-----------------------------

+









=

(EQ. 13)