ISL97649AIRZ datasheet(8/22 Pages) RENESAS

8 / 22 page

ISL97649A

FN7928 Rev 3.00

Page 8 of 22

June 27, 2013

tSU:DAT

Input Data Set-up Time

From SDA exiting the 30% to 70% of VIN

window, to SCL rising edge crossing 30% of

VIN

tHD:DAT

Input Data Hold Time

From SCL rising edge crossing 70% of VIN to

SDA entering the 30% to 70% of VIN window

0ns

tSU:STO

STOP Condition Set-up Time

From SCL rising edge crossing 70% of VIN, to

SDA rising edge crossing 30% of VIN

400

tHD:STO

STOP Condition Hold Time for Read, or

Volatile Only Write

From SDA rising edge to SCL falling edge;

both crossing 70% of VIN

400

CSCL

Capacitive on SCL

5pF

CSDA

Capacitive on SDA

5pF

tWp

Non-Volatile Write Cycle Time

EEPROM Endurance

TA= +25°C

kCyc

EEPROM Retention

TA = +25°C

kHrs

NOTES:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

7. Typical values are for TA = +25°C and VIN = 3.3V.

8. LSB = I V255 - V1I / 254. V255 and V1 are the measured voltages for the DCP register set to FF hex and 01 hex respectively.

9. DNL = I Vi+1 - Vi I / LSB-1,

10. ZS error = (V1 -VMIN) / LSB. VMIN = (VAVDD*R2) * [1-254*R1/(255*20*RSET)]/ (R1+R2).

11. FS error = (V255 - VMAX) / LSB. VMAX= (VAVDD*R2) * [1-0*R1/(255*20*RSET)]/ (R1+R2).

12. Established by design. Not a parametric spec.

13. Boost will stop switching as soon as boost output reaches OVP threshold.

14. Compliance to limits is assured by characterization and design.

Serial Interface Specifications For SCL and SDA Unless Otherwise Noted. (Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 14)

TYP

(Note 7)

MAX

(Note 14)

UNITS

i1 255

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