ISL97649A

FN7928 Rev 3.00

Page 12 of 22

June 27, 2013

Output Capacitor

The output capacitor supplies the load directly and reduces the

ripple voltage at the output. Output ripple voltage consists of two

components:

1. The voltage drop due to the inductor ripple current flowing

through the ESR of the output capacitor.

2. Charging and discharging of the output capacitor.

For low ESR ceramic capacitors, the output ripple is dominated

by the charging and discharging of the output capacitor. The

voltage rating of the output capacitor should be greater than the

maximum output voltage.

Note: Capacitors have a voltage coefficient that makes their

effective capacitance drop as the voltage across them increases.

at a particular voltage and not the manufacturer’s stated value,

measured at 0V.

Table 4 shows some selections of output capacitors.

Compensation

The boost converter of ISL97649A can be compensated by an RC

network connected from the COMP pin to ground. 15nF and 5.5k

RC network is used in the demo board. The larger value resistor

and lower value capacitor can lower the transient overshoot,

however, at the expense of the stability of the loop.

Linear Regulator (LDO)

The ISL97649A includes an LDO with adjustable output. It can

supply current up to 350mA. The output voltage is adjusted by

connection of the ADJ pin.

The efficiency of the LDO depends on the difference between

input voltage and output voltage (Equation 7) by assuming LDO

quiescent current is much lower than LDO output current:

The less difference between input and output voltage, the higher

efficiency it is.

Ceramic capacitors are recommended for the LDO input and

output capacitors. Intersil recommends an output capacitor

within the 1µF to 4.7µF range and a maximum feedback resistor

impedance of 20kΩ. Larger capacitors help to reduce noise and

deviation during transient load change. Some capacitors are

recommended in Table 5.

Supply Monitor Circuit

The Supply Monitor circuit monitors the voltage on VDIV, and sets

open-drain output RESET low when VDIV is below 1.28V (rising)

or 1.22V (falling).

There is a delay on the rising edge, controlled by a capacitor on

CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from

0V to 1.217V by a 10µA current source. Once CD2 exceeds

1.217V, RESET will go tri-state. When VDIV falls below 1.22V,

RESET will become low with a 650Ω pull-down resistance. The

delay time is controlled by Equation 8:

For example, the delay time is 12.17ms if the CD2 = 100nF.

Figure 13 shows the Supply Monitor Circuit timing diagram.

10µH/

2.2Apeak

6.6x7.3x1.2 Cyntec PCME061B-100MS

PCB

space/profile

optimization

TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATION

DIODE

PACKAGE

MFG

PMEG2010ER

20V/1A

SOD123W NXP

MSS1P2U

20V/1A

MicroSMP VISHAY

TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATION

CAPACITOR

SIZE

MFG

PART NUMBER

10µF/25V

1210

TDK

C3225X7R1E106M

10µF/25V

1210

Murata

GRM32DR61E106K

TABLE 2. BOOST CONVERTER INDUCTOR RECOMMENDATION

INDUCTOR

DIMENSIONS

(mm)

MFG

PART

NUMBER

NOTE

–

------------------------

----------------

1

----





+



=

(EQ. 6)

TABLE 5. LDO OUTPUT CAPACITOR RECOMMENDATION

CAPACITOR

SIZE

MFG

PART NUMBER

1µF/10V

0603

TDK

C1608X7R1A105K

1µF/6.3V

0603

MURATA GRM188R70J105K

2.2µF/6.3V

0603

TDK

C1608X7R0J225K

 %



------------------------------







100%



=

(EQ. 7)

121.7k CD2



=

(EQ. 8)

VDIV

RESET

1.28V

1.22V

1.217V

CD2

RESET DELAY TIME IS

CONTROLLED BY CD2

CAPACITOR

FIGURE 13. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM