ISL97649A

FN7928 Rev 3.00

Page 18 of 22

June 27, 2013

Initial VCOM Setting

A 256-step resolution is provided under digital control, which

adjusts the sink current of the output. The output is connected to

an external voltage divider, so that the device will have the

capability to reduce the voltage on the output by increasing the

output sink current. The equations that control the output are

given in the following. The initial setting value is at 128. The WR

write communication. When writing to the EEPROM, VGH needs

to be higher than 12V when AVDD is 8V. Outside these

conditions, writing operations may be not successful. The

minimum resistor value of RSET is determined by the following

equations:

Start-up Sequence

When VIN rising exceeds UVLO, it takes 120µs to read the

settings stored in the chip in order to activate the chip correctly.

After all the settings are written in the registers, VLOGIC starts up

with a 0.5ms soft-start time. When both VLOGIC is in regulation

and EN is high, the boost converter starts up. The Gate Pulse

modulator output VGHM is held low until VDPM is charged to

1.215V. The detailed power on sequence is shown in Figure 21.

Layout Recommendation

The device's performance, including efficiency, output noise,

transient response and control loop stability, is affected by the

PCB layout. PCB layout is critical, especially at high switching

frequency.

Following are some general guidelines for layout:

1. Place the external power components (the input capacitors,

output capacitors, boost inductor and output diodes, etc.) in

close proximity to the device. Traces to these components

should be kept as short and wide as possible to minimize

parasitic inductance and resistance.

3. Loops with large AC amplitudes and fast slew rate should be

made as small as possible.

4. The feedback network should sense the output voltage

directly from the point of load, and be as far away from the LX

node as possible.

5. The power ground (PGND) should be connected at the

ISL97649A exposed die plate area.

6. The exposed die plate, on the underside of the package,

should be soldered to an equivalent area of metal on the PCB.

This contact area should have multiple via connections to the

back of the PCB as well as connections to intermediate PCB

layers, if available to maximize thermal dissipation away from

the IC.

7. To minimize the thermal resistance of the package when

soldered to a multi-layer PCB, the amount of copper track and

ground plane area connected to the exposed die plate should

be maximized and spread out as far as possible from the IC.

The bottom and top PCB areas especially should be

maximized to allow thermal dissipation to the surrounding air.

8. Minimize feedback input track lengths to avoid switching

noise pick-up.

A demo board is available to illustrate the proper layout

implementation.

(EQ. 13)

RSET V_AVDD 20x100

A







IOUT

255 Setting

–

256

-------------------------------------

20 RSET



-----------------------------



=

(EQ. 14)

VOUT



+



--------------------------------

1

255 Setting

–

256

-------------------------------------

20 RSET



-----------------------------



–







=

(EQ. 15)