ADL5202ACPZ-R7 datasheet(4/29 Pages) AD

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ADL5202

Data Sheet

Rev. D | Page 4 of 29

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

POWER-UP INTERFACE

PWUPA, PWUPB pins

Power-Up Threshold

Minimum voltage to enable the device

1.4

Maximum voltage to enable the device

3.3

PWUPx Input Bias Current

μA

GAIN CONTROL INTERFACE

VIH

Minimum/Maximum voltage for a logic high

1.41

3.3

VIL

Maximum voltage for a logic low

0.8

Maximum Input Bias Current

μA

SPI TIMING

LATCHA and LATCHB, SCLK, SDIO, data pins

fSCLK

1/tSCLK

MHz

tDH

Data hold time

tDS

Data setup time

tPW

SCLK high pulse width

POWER INTERFACE

Supply Voltage

4.5

5.5

Quiescent Current, Both Channels

High performance mode

210

TA = 85°C

250

Low power mode

160

TA = 85°C

180

Power-Down Current, Both Channels

PWUPx low

1 The minimum value for a logic high on the PM pin is 2.8 V.

Timing Diagrams

SCLK

___ ___

CSA, CSB

SDIO

tSCLK

tDS

tDS tDH

tPW

tDH

DNC

R/W

FA1

FA0

Figure 2. SPI Interface Read/Write Mode Timing Diagram

tDS

tPW

tDS

tDH

UPDN_DAT

UPDN_CLK

RESET

Figure 3. Up/Down Mode Timing Diagram

LATCHA,

LATCHB

A5 TO A0

B5 TO B0

tDH

Figure 4. Parallel Mode Timing Diagram

ADL5202ACPZ-R7 数据表(PDF) 4 Page - Analog Devices

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