ADL5202

Data Sheet

Rev. D | Page 20 of 29

50Ω

AC

1:3

75Ω

75Ω

1.0µH

5V

1.0µH

5V

33Ω

33Ω

4pF

5V

0.1µF

0.1µF

0.1µF

0.1µF

DIGITAL

INTERFACE

1/2

ADL5202

AD9268

56nH

56nH

Figure 55. Wideband ADC Interfacing Example Featuring One-Half of the ADL5202 and the AD9268

Figure 55 shows one-half of the ADL5202 driving a two-pole,

100 MHz low-pass filter into the AD9268. The AD9268 is

a 16-bit, 125 MSPS analog-to-digital converter with a buffered

wideband input, which presents a 6 kΩ differential input impe-

dance and requires between a 1 V or 2 V input swing to reach

full scale. This example uses the 2 V p-p input. For optimum

performance, the ADL5202 should be driven differentially,

using an impedance transformer or input balun.

–15

–14

–13

–12

–11

–10

–9

–8

–7

–6

–5

–4

–3

–2

–1

0

0

20

40

60

80

100

120

140

160

180

200

FREQUENCY (MHz)

Figure 56. Measured Frequency Response of Wideband

ADC Interface, as Depicted in Figure 55

Figure 55 uses a 1:3 impedance transformer to provide the 150 Ω

input impedance of the ADL5202 with a matched input. The

outputs of the ADL5202 are biased through the two 1 μH

inductors, and the two 0.1 μf capacitors on the outputs decouple

the 5 V inductor voltage from the input common-mode voltage of

the AD9268. The two 75 Ω resistors provide the 150 Ω load to the

ADL5202 whose gain is load dependent. The 56 nH inductors

and 4 pF capacitor constitute the (100 MHz – 1 dB) low-pass

filter. The two 33 Ω isolation resistors suppress any switching

currents from the ADC input sample-and-hold circuitry. The

circuit depicted in Figure 55 provides variable gain, isolation,

filtering, and source matching for the AD9268. Using this circuit

with the ADL5202 in a gain of 20 dB (maximum gain), an SNR

of 69 dB, and an SFDR performance of >86 dBc is achieved at

100 MHz, as shown in Figure 57.

0

–15

–30

–45

–60

–75

–90

–105

–120

–150

–135

0

6

12

18

24

30

36

42

48

54

60

FREQUENCY (MHz)

SNR = 69dB

SFDR = 86dBc

NOISE FLOOR = –108dB

FUND = –1.035dBFS

SECOND = –89.17dBc

5

4

+

6

3

2

Figure 57. Measured Single-Tone Performance of the

Circuit in Figure 55 for a 100 MHz Input Signal

0

6

12

18

24

30

36

42

48

54

60

FREQUENCY (MHz)

FUNDAMENTAL1 = –7.127dBFS

FUNDAMENTAL2 = –7.039dBFS

2F1 – F2 = –91.818dBc

2F2 – F1 = –87.083dBc

NOISE FLOOR = –109.57dB

0

–15

–30

–45

–60

–75

–90

–105

–120

–150

–135

2F1 + F2

2F1 – F2

2F2 – F1

F2 – F1

+

F1 + F2

2F2 + F1

Figure 58. Measured Two-Tone Performance of the

Circuit in Figure 55 for a 100 MHz Input Signal