ADL5202ACPZ-R7 datasheet(19/29 Pages) AD

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Data Sheet

ADL5202

Rev. D | Page 19 of 29

APPLICATIONS INFORMATION

BASIC CONNECTIONS

Figure 54 shows the basic connections for operating the ADL5202.

A voltage between 4.5 V and 5.5 V should be applied to the VPOS

pins. Each supply pin should be decoupled with at least one low

inductance, surface-mount ceramic capacitor of 0.1 μF, placed

as close as possible to the device.

The outputs of the ADL5202 must be pulled up to the positive

supply with 1 μH RF chokes. The differential outputs are biased

to the positive supply and require ac coupling capacitors, pref-

erably 0.1 μF. Similarly, the input pins are at bias voltages of

about 1.6 V above ground and should be ac-coupled as well.

The ac coupling capacitors and the RF chokes are the principle

limitations for operation at low frequencies.

The digital pins (mode control pins, associated SPI and parallel

gain control pins, PM, PWUPA, and PWUPB) operate on a voltage

of 3.3 V.

To enable each channel of the ADL5202, the PWUPA or PWUPB

pin must be pulled high (1.4 V≤ PWUPA/PWUPB ≤ 3.3 V).

Taking PWUPA or PWUPB low puts the channels of the ADL5202

in sleep mode, reducing current consumption to approximately

7 mA per channel at ambient.

ADC DRIVING

The ADL5202 is a highly linear, variable gain amplifier that

is optimized for ADC interfacing. The output IMDs and noise

floor remain constant throughout the 31.5 dB gain range.

This is a valuable feature in a variable gain receiver where it is

desirable to maintain a constant instantaneous dynamic range

as the receiver range is modified. The output noise is 18 nV/√Hz,

which is compatible with 14- or 16-bit ADCs. The two-tone

IMDs are usually greater than −100 dB for −1 dBm into 150 Ω

or 2 V p-p output. The 150 Ω output impedance makes the task

of designing a filter for the high input impedance ADCs more

straightforward.

0.1µF

3.3V

0.1µF

BALANCED

SOURCE

0.1µF

BALANCED

SOURCE

CHANNEL A

GAIN CONTROL INTERFACE

CHANNEL B

GAIN CONTROL INTERFACE

GAIN MODE

INTERFACE

0.1µF

VPOS

1µH

MODE1

MODE0

GND

SIDO/B5

SCLK/B4

VPOS

CSA/A3

GS1/CSB/

ADL5202

EXPOSED

PADDLE

VOUTB–

VOUTB+

VOUTA+

VOUTA–

0.1µF

BALANCED

LOAD

0.1µF

VPOS

1µH

BALANCED

LOAD

3.3V

Figure 54. Basic Connections

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