ADL5202

Data Sheet

Rev. D | Page 6 of 29

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

EXPOSED

PADDLE

NOTES

1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO

A LOW IMPEDANCE GROUND PAD.

1

2

A4

3

A5

4

MODE1

5

MODE0

6

PM

7

GND

8

SIDO/B5

9

SCLK/B4

10

23 VPOS

24 VPOS

25 VPOS

26 VPOS

27 VPOS

28 VPOS

29

30

22

21

PIN 1

INDICATOR

CSA/A3

GS1/CSB/B3

ADL5202

VOUTB–

VOUTB+

VOUTA+

VOUTA–

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 3. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

CSA/A3

Channel A Select (CSA). When serial mode is enabled, a logic low (0 V ≤ CSA ≤ 0.8 V) selects Channel A.

Bit 3 for Channel A Parallel Gain Control Interface (A3).

2

A4

Bit 4 for Channel A Parallel Gain Control Interface.

3

A5

Bit 5 (MSB) for Channel A Parallel Gain Control Interface.

4

MODE1

MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode.

5

MODE0

LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode.

6

PM

Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high

(2.8 V ≤ PM ≤ 3.3 V) enables low power mode.

7, 18, 33, EP

GND

Ground. The exposed paddle (EP) must be connected to a low impedance ground pad.

8

SDIO/B5

Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing

to the SPI port.

Bit 5 for Channel B Parallel Gain Control Interface (B5).

9

SCLK/B4

Serial Clock Input in SPI Mode (SCLK).

Bit 4 for Channel B Parallel Gain Control Interface (B4).

10

GS1/CSB/B3

MSB for Gain Step Size Control in Up/Down Mode (GS1).

Channel B Select (CSB). When serial mode is enabled, a logic low (0 V ≤ CSB≤ 0.8 V) selects Channel B.

Bit 3 for Channel B Parallel Gain Control Interface (B3).

11

GS0/FA_B/B2

LSB for Gain Step Size Control in Up/Down Mode (GS0).

Fast Attack (FA_B). In serial mode, a logic high (1.4 V ≤ FA_B ≤ 3.3 V) attenuates Channel B according to

the FA setting in the SPI word.

Bit 2 for Channel B Parallel Gain Control Interface (B2).

12

UPDN_CLK_B/B1

Clock Interface for Channel B Up/Down Function (UPDN_CLK_B).

Bit 1 for Channel B Parallel Gain Control Interface (B1).

13

UPDN_DAT_B/B0

Data Pin for Channel B Up/Down Function (UPDN_DAT_B).

Bit 0 for Channel B Parallel Gain Control Interface (B0).

14

LATCHB

Channel B Latch. A logic low (0 V ≤ LATCHB ≤ 0.8 V) allows gain changes on Channel B. A logic high

(1.4 V ≤ LATCHB ≤ 3.3 V) prevents gain changes on Channel B.