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M69AW024B 数据表(PDF) 17 Page - STMicroelectronics |
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M69AW024B 数据表(HTML) 17 Page - STMicroelectronics |
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17 / 29 page ![]() 17/29 M69AW024B Table 8. Write Mode AC Characteristics Symbol Alt. Parameter M69AW024B Unit –60 –70 Min Max Min Max tAVEL (2) tAS Address Set-up Time to Chip Enable Low 0 0 ns tAVWL tAS Address Set-up Time to Write Enable Low 0 0 ns tAXGL1 (3,4) tOEH Address Invalid to Output Enable Low 25 1000 35 1000 ns tAXGL2 (5) tOEH(ABS) Address Invalid to Output Enable Low (absolute) 12 15 ns tBLEL tBS LB, UB Set-up Time to Chip Enable Low –5 –5 ns tBLWL tBS LB, UB Set-up Time to Write Enable Low –5 –5 ns tDVEH tDS Data Set-up Time to Chip Enable High 15 20 ns tDVWH tDS Data Set-up Time to Write Enable High 15 20 ns tEHBH tBH LB, UB Hold Time from Chip Enable High –5 –5 ns tEHDX tDH Input Data Hold Time from Chip Enable High 0 0 ns tEHEL1 (9,10) tWRC Chip Enable High Pulse Width to Chip Enable Low 20 20 ns tEHEL2 (10) tCP Chip Enable High Pulse Width to Chip Enable Low 10 12 ns tEHWH tWH Write Enable Low Hold Time 0 0 ns tEHWL tWH Write Enable High Hold Time 0 0 ns tELAX (2) tAH Address Hold Time from Chip Enable Low 35 40 ns tELEH1 (1,8) tCW Chip Enable Write Pulse Width 45 50 ns tELEH2 (1,9,10) tWRC Chip Enable Write Recovery Time 20 20 ns tELEL tWC Chip Enable Write Cycle Time 80 90 ns tELWL tCS Chip Enable Write Set-up Time 0 1000 0 1000 ns tGHAX (7) tOHAH Address Hold Time from Output Enable High –5 –5 ns tGHBH tBH LB, UB Hold Time from Output Enable High –5 –5 ns tGHEL (6) tOHCL Output Enable High to Chip Enable Low Set-up Time –5 –5 ns tGHWL (3) tOES Output Enable Set-up Time 0 1000 0 1000 ns tWHAV (1,3,9,10) tWR Write Enable High to Address Valid 20 1000 20 1000 ns tWHBH tBH LB, UB Hold Time from Write Enable High –5 –5 ns tWHDX tDH Input Data Hold Time from Write Enable High 0 0 ns tWHEH tCH Chip Enable Write Hold Time 0 1000 0 1000 ns tWHEL tWS Write Enable High Set-up Time 0 0 ns tWHWL (1,3,9,10) tWR Write Enable Write Recovery Time to Write Enable Low 20 1000 20 1000 ns tWLAV tWC Write Enable Low to Address Valid Write Cycle Time 80 90 ns tWLAX (2) tAH Address Hold Time from Write Enable Low 35 40 ns |
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