M69AW024B datasheet(25/29 Pages) STMICROELECTRONICS

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M69AW024B

Figure 22. Power-up Mode AC Waveforms - 3

Note: Both E1 and E2 must go High as VCC reaches VCC(min). If not, the timings provided in Power-Up Mode AC Waveforms 1 (Figure 20.)

or Power-Up Mode AC Waveforms 2 (Figure 21.) should be used to ensure proper operation.

Table 10. Low VCC Data Retention Characteristics

Note: 1. TA = –30 to 85°C

2. All other Inputs at VIH ≥ VCC –0.2V or VIL ≤0.2V.

3. See Figure 23. for measurement points.

Figure 23. Low VCC Data Retention AC Waveforms

Symbol

Parameter

Test Condition1

Min

Max

Unit

VDR

(2)

Supply Voltage (Data Retention)

E1 = E2

≥ VCC –0.2V, or

= VIH and E2 = VIH

2.3

3.5

ICCDR

Supply Current (Data Retention)

VCC = VDR, VIN ≤0.2V or ≥ VCC –0.2V,

= ≥ VCC –0.2V and E2 ≥ VCC –0.2V,

IOUT = 0mA

µA

tCDR

(2,3)

Chip deselected to Data Retention

Time

VCC = 2.7V

0ns

(3)

Operation Recovery Time

VCC = 2.7V

100

∆V/∆t (3)

VCC Voltage Transition Time

0.2

V/µs

AI08054C

VCC

VCC min

tEHEL

AI07408

DATA RETENTION MODE

∆V/∆t

3.5V

tCDR

2.7V

2.3V

E1 and E2

≥ VDD – 0.2V or VIH(min)

VCC

0.4V

VSS

∆V/∆t

Data Bus must be Hi-Z

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