M69AW024B datasheet(4/29 Pages) STMICROELECTRONICS

4 / 29 page

M69AW024B

4/29

SUMMARY DESCRIPTION

The M69AW024B is a 16 Mbit (16,777,216 bit)

CMOS memory, organized as 1,048,576 words by

16 bits, and is supplied by a single 2.7V to 3.3V

supply voltage range.

M69AW024B is a member of STMicroelectronics

PSRAM memory family, based on the one-transis-

tor per-cell architecture. These devices are manu-

factured using dynamic random access memory

cells, to minimize the cell size, and maximize the

amount of memory that can be implemented in a

given area.

However, through the use of internal control logic,

the device is fully static in its operation, requiring

no external clocks or timing strobes, and has a

standard Asynchronous SRAM Interface.

The internal control logic of the M69AW024B han-

dles the periodic refresh cycle, automatically, and

without user involvement.

Write cycles can be performed on a single byte by

using Upper Byte Enable (UB) and Lower Byte En-

able (LB).

The device can be put into standby mode using

Chip Enable (E1) or in deep power down mode by

using Chip Enable (E2).

Power-Down mode achieves a very low current

consumption by halting all the internal activities.

Since the refresh circuitry is halted, the duration of

the power-down should be less than the maximum

period for refresh, if the user has not finished with

the data contents of the memory.

Figure 2. Logic Diagram

Table 1. Signal Names

AI07406

A0-A19

DQ0-DQ15

VCC

M69AW024B

VSS

A0-A19

Address Input

DQ0-DQ15

Data Input/Output

E1, E2

Chip Enable, Power Down

Output Enable

Write Enable

Upper Byte Enable

Lower Byte Enable

VCC

Supply Voltage

VSS

Ground

Not Connected

(no internal connection)

M69AW024B 数据表(PDF) 4 Page - STMicroelectronics

M69AW024B 数据表(HTML) 4 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

数据表下载