T48C893 datasheet(21/82 Pages) ATMEL

21 / 82 page

T48C893

Rev. A4, 22-Jan-02

21 (82)

Peripheral Modules

4.1

Addressing Peripherals

Accessing the peripheral modules takes place via the I/O

bus (see figure 21). The IN or OUT instructions allow di-

rect addressing of up to 16 I/O modules. A dual register

addressing scheme has been adopted to enable direct ad-

dressing of the ”primary register”. To address the

”auxiliary register”, the access must be switched with an

”auxiliary switching module”. Thus a single IN (or OUT)

to the module address will read (or write) into the module

primary register. Accessing the auxiliary register is per-

formed with the same instruction preceded by writing the

module address into the auxiliary switching module. Byte

wide registers are accessed by multiple IN- (or OUT-)

instructions. For more complex peripheral modules, with

a larger number of registers, extended addressing is used.

In this case a bank of up to 16 subport registers are indi-

rectly addressed with the subport address. The first

OUT-instruction writes the subport address to the sub-

address register, the second IN- or OUT-instruction reads

data from or writes data to the addressed subport.

Subaddress Reg.

Subport 0

Subport 1

Subport Fh

Subport Eh

I/O bus

Aux. Reg.

Primary Reg.

Bank of

Primary Regs.

Primary Reg.

(Address Pointer)

Auxiliary Switch

Module

Indirect Subport

Access

Dual Register

Access

Single Register

Access

to other modules

Address(M2) Address(ASW) OUT

Aux._Data

Address(M2) OUT

Prim._Data

Address(M2) OU T

(Primary Register Write)

Prim._Data Address(M3) O UT

(P rima ry Register Write)

Addr.(SPort)

Addr.(M1)

OUT

(Subport Register Write)

SPort_Data

Addr.(M1)

OUT

Example of

qFORTH

Program

Code

Addr.(Mx) = Module Mx Addr ess

Aux._Data = da ta to be written into Auxilia ry Register

Prim._Data = data to be written into P rimar y Register.

Addr.(SPort) Addr.(M1)

OUT

(Subport Register Read)

Addr.(M 1)

Address(M2) Address(ASW) OUT

Address(M 2)

(Auxiliary Register Rea d)

Address(M 2)

(Primary Register Rea d)

Address(M3) IN

(Prima ry Register Read)

Addr.(ASW) = Auxiliary Switch Module Address

Addr.(SPort) Addr.(M1)

OUT

(Subport Register Write Byte)

SPort_Data(lo) Addr.(M1)

OUT

Addr.(SPort) Addr.(M1)

OUT

(Subport Register Rea d Byte)

Addr.(M 1)

SPort_Data(hi) Addr.(M1) OUT

Addr.(M 1)

SPort_Data(lo) = data to be written into SubP ort (low nibble)

SPort_Data(hi) = da ta to be written into Subport (high nibble)

Addr.(SPort) = Subport Address

Address(M2) Address(ASW) OUT

Aux._Data(lo) Address(M2) OUT

(Auxiliary Register Write Byte)

Aux._Data(hi) Address(M2) OUT

Aux._Data (lo)= data to be written into Auxiliary Register (low nibble)

Aux._Data (hi) = da ta to be written into Auxiliar y Register (high nibble)

( Auxiliary Register Write )

13357

(hi)

(lo)

(lo) = SPort_Data (low nibble)

(hi) = SPort_Data (high nibble)

Module ASW

Module M1

Module M2

Module M3

Figure 21. Example of I/O addressing

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