T48C893 datasheet(56/82 Pages) ATMEL

56 / 82 page

T48C893

Rev. A4, 22-Jan-02

56 (82)

4 3210

76 54321 0

msb

lsb

rx data 1

rx data 2

rx data 3

msb

lsb

msb

lsb

Read SRB

(rx data 2)

Read SRB

(rx data 3)

Read SRB

(rx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

13825

765

43210

7 6 5

7654

Figure 61. Example of 8-bit synchronous receive operation

9-bit Shift Mode (I2C compatible)

In the 9-bit shift mode, the SSI is able to handle the I2C

protocol (described below). It always operates as an I2C

master device, i.e., SC is always generated and output by

the SSI. Both the I2C start and stop conditions are auto-

matically generated whenever the SSI is activated or

deactivated by the SIR–bit. In accordance with the I2C

protocol, the output data is always changed in the clock

low phase and shifted in on the high phase.

Before activating the SSI (SIR=0) and commencing an

I2C dialog, the appropriate data direction for the first

word must be set using the SDD control bit. The state of

this bit controls the direction of the data port (BP43 or

MCL_SD). Once started, the 8 data bits are, depending on

the selected direction, either clocked into or out of the

shift register. During the 9th clock period, the port

direction is automatically switched over so that the

corresponding acknowledge bit can be shifted out or read

in. In transmit mode, the acknowledge bit received from

the slave device is captured in the SSI Status Register

(TACK ) where it can be read by the controller. and in

receive mode, the state of the acknowledge bit to be

returned to the slave device is predetermined by the SSI

Status Register (RACK ).

Changing the directional mode (TX/RX) should not be

performed during the transfer of an I2C telegram. One

should wait until the end of the telegram which can be

detected using the SSI interrupt (IFN =1) or by

interrogating the ACT status.

A 9-bit telegram, once started will always run to

completion and will not be prematurely terminated by the

SIR bit. So, if the SIR–bit is set to ‘1’ in mit telegram, the

SSI will complete the current transfer and terminate the

dialog with an I2C stop condition.

T48C893 数据表(PDF) 56 Page - ATMEL Corporation

T48C893 数据表(HTML) 56 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表下载

链接网址

T48C893 数据表(PDF) 56 Page - ATMEL Corporation

T48C893 数据表(HTML) 56 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

数据表 下载

链接网址

数据表下载