HMC6832

Data Sheet

Rev. C | Page 16 of 23

–170

–169

–168

–167

–166

–165

–164

–163

–162

–161

–160

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

SUPPLY VOLTAGE (V)

LVDS

LVPECL

Figure 28. Phase Noise Floor vs. Supply Voltage for LVPECL and LVDS,

–170

–169

–168

–167

–166

–165

–164

–163

–162

–161

–160

–60

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

3GHz

2GHz

1GHz

Figure 29. LVPECL 2.5 V, 150 Ω, Phase Noise Floor vs. Temperature for

Various Carrier Frequencies

–170

–169

–168

–167

–166

–165

–164

–163

–162

–161

–160

–60

–40

–20

0

20

40

60

80

100

TEMPERATURE (°C)

2GHz

1GHz

3GHz

Figure 30. LVDS Phase Noise Floor vs. Temperature for Various Carrier Frequencies

–35

–30

–25

–20

–15

–10

–5

0

0

2

4

6

8

10

FREQUENCY (GHz)

DIFFERENTIAL, 2.5V

SINGLE-ENDED, 2.5V

DIFFERENTIAL, 3.3V

SINGLE-ENDED, 3.3V

Figure 31. LVDS/LVPECL S Parameters (S11), Network Analyzer Gating Used

to Remove Input and Output Impedance Mismatch and Board Loss

–110

–100

–90

–80

–60

–70

–50

–40

–30

0

2

4

6

8

10

FREQUENCY (GHz)

DIFFERENTIAL, 2.5V

SINGLE-ENDED, 2.5V

DIFFERENTIAL, 3.3V

SINGLE-ENDED, 3.3V

Figure 32. LVPECL S Parameters (S12), Network Analyzer Gating Used to

Remove Input and Output Impedance Mismatch and Board Loss

–110

–100

–90

–80

–60

–70

–50

–40

–30

0

2

4

6

8

10

FREQUENCY (GHz)

DIFFERENTIAL, 2.5V

SINGLE-ENDED, 2.5V

Figure 33. LVDS S Parameters (S12), Network Analyzer Gating Used to

Remove Input and Output Impedance Mismatch and Board Loss