HMC6832

Data Sheet

Rev. C | Page 20 of 23

OUTP7

VAC_REF

4mA

4mA

OUTN7

LVDS

OUTP6

4mA

4mA

OUTN6

LVDS

OUTP5

4mA

4mA

OUTN5

LVDS

OUTP4

4mA

4mA

OUTN4

LVDS

OUTP3

4mA

4mA

OUTN3

LVDS

OUTP2

4mA

4mA

OUTN2

LVDS

OUTP1

4mA

4mA

2mA

OUTN1

LVDS

OUTP0

4mA

4mA

OUTN0

LVDS

Figure 46. Output Stage Block Diagram

A number of choices are available for connecting the LVPECL

drivers and receivers. There are compromises between matching

performance, common-mode levels, and signal swing. For clocking

applications, the user often has the option of using ac coupling,

unlike in many datapath situations. Figure 47 shows a simplified

interface schematic between an LVPECL output and an input

stage, where various options and trade-offs for the termination

components are provided (see Table 11). The Analog Devices,

Inc., evaluation board has a great deal of flexibility in how the

inputs/outputs are configured. Several configurations are shown

in the Applications Information section.

VDD = 2.5V/3.3V

OUTP

OUTN

LVPECL

HMC6832

Figure 47. Recommended Interface Diagram

Table 11. Interface Values

Interface Value

Description

DC current termination for LVPECL

output stage

150 Ω

Analog Devices evaluation board

default, standard LVPECL termination

voltages

200 Ω

Reduced current, no performance

degradation

300 Ω

Further reduced current, lower output

power but flatter frequency response

Open

If using internal dc termination

network at the receiver

Large Capacitor

Analog Devices evaluation board

default, when ac coupling is used