12

PRELIMINARY

R00A

IX6611

shoot-through in the large output P-channel and

N-channel devices.

The Gate Control Logic block also receives power

supply status, IGBT over-current status, and IGBT

collector over-voltage status signals. Based on these

signals the output stage is conditioned accordingly as

shown in Figure 2 on page 9, Figure 3 on page 9,

Figure 4 on page 10 and Figure 5 on page 10.

If a supply under-voltage or a supply over-voltage fault

event is detected during the leading edge of the input

PWM gate drive cycle, then the driver is disabled for

the entire duration of the cycle. Normal operation

resumes at the beginning of the next cycle only if there

is no supply fault condition.

If an IGBT over-current fault occurs during the ON

time of the PWM cycle, then the IGBT driver output is

forced low for the remainder of the cycle. Normal

operation resumes at the beginning of the next PWM

gate drive cycle.

During the OFF time of the IGBT driver, if an IGBT

collector over-voltage fault occurs, then for the

remainder of the cycle the output PFET is turned off

and the output NFET state is controlled by the ACL

comparator as shown in the Figure 5 on page 10.

Normal operation resumes at the beginning of the next

PWM gate drive cycle.

3.1.4

IGBT Drive Outputs

IX6611 contains separate 10A peak source and sink

outputs. Separated sink and source outputs allow

independent gate charge and discharge control

without an external diode. The internal dead-time

circuit eliminates the cross conduction of the source

and sink outputs.

3.1.5

Over Current Comparator

IX6611 contains an Over Current Comparator (OC

COMP) with a 300mV threshold. This comparator is

used for sensing over-current conditions in the

external IGBT.

Emitter current sense can be implemented either by

using a low value current shunt or an IGBT with a

secondary current sense output.

The current-sense method works well for high gain

IGBTs that do not have inherent short circuit

protection. Careful application board layout is

mandatory due to low sense voltage.

Traditional de-saturation protection can also be

implemented using a large ratio resistor divider

connected across the collector and the emitter. A

noise filter (RC) at the current sense input may be

required due to low sense voltage.

3.1.6

Leading Edge Blanking Circuit

To prevent false tripping of the OC Comparator, its

input is grounded for a fixed amount of time during the

turn-on of the IGBT.

Leading Edge Blanking Circuit sets the blanking time

and it is programmable through an external capacitor.

The OC Comparator input is also grounded during the

off time of the driver.

3.1.7

Active Clamp Comparator

IX6611 contains an Active Clamp Comparator (ACL

COMP) with a 3.1V threshold that can be used for

implementing an advanced active clamping technique

as shown in application circuit diagram Figure 6 on

During the turn off of the IGBT, the ACL comparator

can detect an over voltage, if the collector voltage

rises above the breakdown voltage of the diode

connected at the collector. In the over voltage

condition the ACL comparator forces the gate driver

output to a tri-state condition and the IGBT starts to

turn on due to the break down diode current charging

the IGBT gate. Once the IGBT turns on, its collector

voltage falls, the diode recovers from break down, and

the ACL comparator turns on the NMOS output and

forces the IGBT gate low. This sequence may repeat

several times until the energy in the external

inductance is dissipated.

ACL comparator is active only when the driver output

PFET is OFF.

3.1.8

Thermal Shutdown (THSD)

IX6611 contains a Thermal Shutdown circuit to protect

the device against the damage due to excessive die

temperature. When the junction temperature exceeds

150°C, the input signals to the gate driver and the ACL

comparator are disabled and the gate driver output is

forced low. Device resumes normal operation when

the junction temperature falls below 130°C.

3.1.9

Output Fault Pulse Generator

An IGBT over current fault event can occur any time

during the ON time of the gate drive signal. When an