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IX6611TR 数据表(PDF) 13 Page - IXYS Corporation |
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IX6611TR 数据表(HTML) 13 Page - IXYS Corporation |
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13 / 15 page ![]() IX6611 R00A PRELIMINARY 13 over current occurs the Output Faults Pulse Generator creates a narrow 200ns pulse that will be used by the Fault Control Logic to communicate the fault condition to the primary side across the barrier. 3.1.10 5V Regulator The 5V regulator provides power to the internal low voltage circuits that are referenced to VEE. Regulator is powered from VCC and VEE and its output voltage is referenced to VEE. An external bypass capacitor is required to provide the transient currents. 3.1.11 Under Voltage and Over Voltage Lockout IX6611 contains an Under Voltage Lockout Comparator (UVLO COMP) and an Over Voltage Lockout Comparator (OVLO COMP). These comparators monitor the positive power supply terminal “VCC” with respect to “COM” terminal. At the beginning of each PWM cycle, if the difference in power supply voltage (VCC-VCOM) is below the UVLO threshold or above the OVLO threshold the gate driver output is disabled (driven low) for that PWM cycle. Once the PWM cycle starts with no power supply faults then the gate driver is enabled and the UVLO and OVLO faults are ignored for the reminder of the cycle. Power supply fault are not latched. Normal operation resumes automatically on the next PWM input cycle after the power supply recovers from the fault condition. The UVLO circuit is operational at VCC no greater than 3V and it keeps the gate driver output low until VCC is raises above the UVLO threshold. 3.1.12 Fault Control Logic Fault information is communicated to the primary side through the pulse transformer interface. Fault Control Logic provides the gate drive to the high current switches connected to the primary terminals of the pulse transformer. Narrow pulses are used to drive the high current switches. Based on the fault type, the fault control logic selects the narrow pulses either from the input interface or from the output fault pulse generator and drives the appropriate high current switch. UVLO fault condition is communicated to the primary side by driving the FLT1 high current switch on the leading edge of the PWM gate drive ON cycle. OVLO fault condition is communicated to the primary side by driving the FLT1 high current switch on the leading edge and the FLT2 high current switch on the trailing edge of the PWM gate drive ON cycle. The primary side recognizes the OVLO fault condition if and only if both FLT1 and FLT2 flags are set. IGBT Over Current condition is communicated to the primary side by driving the FLT2 high current switch with a pulse from the output fault pulse generator. |
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