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IX6611TR 数据表(PDF) 8 Page - IXYS Corporation

部件名 IX6611TR
功能描述  IGBT Gate Driver
PDF  15 Pages
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制造商  IXYS [IXYS Corporation]
网页  http://www.ixys.com
标志 IXYS - IXYS Corporation

IX6611TR 数据表(HTML) 8 Page - IXYS Corporation

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8
PRELIMINARY
R00A
IX6611
1.5.12
Fault Outputs and Control Logic
VCC=PVCC=15V, VEE=PVEE= -5V.
1.5.13
IGBT Driver Output
VCC=PVCC=15V, VEE=PVEE= -5V.
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Fault signal transformer primary switch sink
resistance
RFLT1, RFLT2
VDD=0V, measured at FLT1 and FLT2
terminals @ ISINK = 100mA
-1
2
W
Fault signal transformer primary switch peak sink
current
IPK_FLT1,
IPK_FLT2
VDD=0V, measured at FLT1 and FLT2
terminals 200ns pulse
(Characterized but not production tested)
0.7
1
-
A
Fault signal transformer primary switch low level
output voltage
VOL_FLT1,
VOL_FLT2
VDD=0V, measured at FLT1 and FLT2
terminals with 5
 pull-up resistance
connected to VDD
-0.5
1.5
V
Fault signal transformer primary switch off-state max
drain voltage
VDSMAX_FLT1
VDSMAX_FLT2
@ IDS_LEAK=1uA
15
-
-
V
Fault signal pulse width
TPW_FLT1
TPW_FLT2
Measured at FLT1 and FLT2 terminals with
100
 pull-up and C
L=50pF resistance
connected to VDD
(characterized but not production tested)
100
200
400
ns
Parameter
Symbol
Conditions
Min
Typ
Max
Units
High level output voltage
VOHP
ISOURCE=100mA
Measured at OUTP terminal
VCC-0.15
--
V
Low level output voltage
VOLN1
ISINK=100mA
Measured at OUTN terminal
--
0.15
V
Output source resistance
ROH
ISOURCE=100mA
Measured at OUTP terminal
-0.8
1.7
Output sink resistance
ROL
ISINK=100mA
Measured at OUTN terminal
-0.7
1.5
Output peak source and sink current
IPK_SRC,
IPK_SNK
@ TA=25°C, CLOAD=330nF
Measured at OUTP and OUTN
terminals
-±10
-
A
Continuous output current
IDC
@ TA=25°C, measured at OUTP
and OUTN terminals
(limited by package power dissipation)
information parameter
-±2
-
A
On-time propagation delay
tON_DLY
CLOAD=10nF
Measured from RCVP to OUTP
-50
125
ns
Off-time propagation delay
tOFF_DLY
CLOAD=10nF
Measured from RCVN to OUTN
-50
125
ns
High impedance state delay time
tTRI_DLY
RLOAD=50 , CLOAD=No load
-300
-
ns
High impedance PFET leakage
IPLEAK
--
<1
10
A
High impedance NFET lockage
INLEAK
--
<2
20
A



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