USB97C201 datasheet(9/59 Pages) SMSC

9 / 59 page

SMSC DS – USB97C201

Page 9

Rev. 03/25/2002

PRELIMINARY

4.0 BLOCK DIAGRAM

Address

USB 2.0 PHY

( Transceiver )

FAST 8051

CPU CORE

ATA-66

Interface

MEM/IO Bus

29pins

GPIO

8 pins

Configuration and Control

Clock Generation

SIE

( Serial Interface Engine )

Program Memory/ IO

Bus

Interrupt Controller

Latch phase 0

Latch phase 1

Latch phase 2

60MHz

32 Bit

Future phase 3

Osc

Address

64 Bytes EP0TX

64 Bytes EP0RX

64 Bytes EP1TX

64 Bytes EP1RX

Auto address generators

Data @ 32 bit

15MHz

SIE Control Regs

Address

EP0RX_BC

EP1RX_BC

RAMRD_A/B

EP0TX_BC

RAMWR_A/B

ATA/ATAPI

Drive

32 bit 15MHz Data Buss

CLOCKOUT

12 MHz

OPTIONAL

External PHY

512 Bytes EP2 TX/RX Buffer A

1.25KB

SRAM

768 Byte

Program/Scratchpad

SRAM

Granted SRAM access

during Phase 0

Granted SRAM access during Phase 1

Granted SRAM access

during Phase 2

EP1TX_BC

512 Bytes EP2 TX/RX Buffer B

USB97C201 数据表(PDF) 9 Page - SMSC Corporation

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USB97C201 数据表(PDF) 9 Page - SMSC Corporation

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