AD5624BCPZ-R2 datasheet(5/23 Pages) AD

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Data Sheet

AD5624/AD5664

Rev. A | Page 5 of 23

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).

VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.

Table 4.

Limit at TMIN, TMAX

Parameter1

VDD = 2.7 V to 5.5 V

Unit

Conditions/Comments

t12

ns min

SCLK cycle time

ns min

SCLK high time

ns min

SCLK low time

ns min

SYNC to SCLK falling edge setup time

ns min

Data setup time

ns min

Data hold time

ns min

SCLK falling edge to SYNC rising edge

ns min

Minimum SYNC high time

ns min

SYNC rising edge to SCLK fall ignore

t10

ns min

SCLK falling edge to SYNC fall ignore

1 Guaranteed by design and characterization, not production tested.

2 Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V.

TIMING DIAGRAM

DB0

DB23

t10

SCLK

SYNC

DIN

Figure 2. Serial Write Operation

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