Data Sheet

AD5624/AD5664

Rev. A | Page 19 of 23

MICROPROCESSOR INTERFACING

AD5624/AD5664 to Blackfin® ADSP-BF53x Interface

Figure 36 shows a serial interface between the AD5624/AD5664

and the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x

processor family incorporates two dual channel synchronous

serial ports, SPORT1 and SPORT0, for serial and multiprocessor

communications. Using SPORT0 to connect to the AD5624/

AD5664, the setup for the interface is as follows. DTOPRI drives

the DIN pin of the AD5624/AD5664, while TSCLK0 drives the

SCLK of the device. The SYNC is driven from TFS0.

AD5624/

SYNC

TFS0

DIN

DTOPRI

SCLK

TSCLK0

Figure 36. Black

fin ADSP-BF53x Interface to AD5624/AD5664

AD5624/AD5664 to 68HC11/68L11 Interface

Figure 37 shows a serial interface between the AD5624/AD5664

and the 68HC11/68L11 microcontroller. SCK of the 68HC11/

68L11 drives the SCLK of the AD5624/AD5664, while the MOSI

output drives the serial data line of the DAC.

The SYNC signal is derived from a port line (PC7). The setup

conditions for correct operation of this interface are as follows.

The 68HC11/68L11 is configured with its CPOL bit as a 0 and

its CPHA bit as a 1. When data is being transmitted to the DAC,

the SYNC line is taken low (PC7). When the 68HC11/68L11 is

configured as described previously, data appearing on the MOSI

output is valid on the falling edge of SCK. Serial data from the

68HC11/68L11 is transmitted in 10-bit bytes with only eight

falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5624/AD5664,

PC7 is left low after the first eight bits are transferred, and a

second serial write operation is performed to the DAC; PC7 is

taken high at the end of this procedure.

AD5624/

SYNC

PC7

SCLK

SCK

DIN

MOSI

Figure 37. 68HC11/68L11 Interface to AD5624/AD5664

AD5624/AD5664 to 80C51/80L51 Interface

Figure 38 shows a serial interface between the AD5624/AD5664

and the 80C51/80L51 microcontroller. The setup for the interface

is as follows. TxD of the 80C51/80L51 drives SCLK of the AD5624/

AD5664, while RxD drives the serial data line of the device. The

SYNC signal is derived from a bit-programmable pin on the port.

In this case, port line P3.3 is used. When data is transmitted to

the AD5624/AD5664, P3.3 is taken low. The 80C51/80L51

transmits data in 10-bit bytes only; thus only eight falling clock

edges occur in the transmit cycle. To load data to the DAC, P3.3

is left low after the first eight bits are transmitted, and a second

write cycle is initiated to transmit the second byte of data. P3.3

is taken high following the completion of this cycle. The 80C51/

80L51 output the serial data in a format that has the LSB first. The

AD5624/AD5664 must receive data with the MSB first. The 80C51/

80L51 transmit routine takes this into account.

AD5624/

SYNC

P3.3

SCLK

TxD

DIN

RxD

Figure 38. 80C51/80L51 Interface to AD5624/AD5664

AD5624/AD5664 to MICROWIRE Interface

Figure 39 shows an interface between the AD5624/AD5664 and

any MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and is clocked into the

AD5624/AD5664 on the rising edge of the SK.

AD5624/

SYNC

CS

SCLK

SK

DIN

SO

Figure 39. MICROWIRE Interface to AD5624/AD5664