Data Sheet

AD5624/AD5664

Rev. A | Page 17 of 23

SOFTWARE RESET

The AD5624/AD5664 contain a software reset function.

Command 110 is reserved for the software reset function (see

Table 7). The software reset command contains two reset modes

that are software programmable by setting Bit DB0 in the control

register. Table 9 shows how the state of the bit corresponds to

the software reset modes of operation of the devices.

Table 9. Software Reset Modes for the AD5624/AD5664

DB0

Registers Reset to Zero

0

DAC register

Input shift register

1 (Power-On Reset)

DAC register

Input shift register

LDAC register

Power-down register

POWER-DOWN MODES

The AD5624/AD5664 contain four separate modes of operation.

Command 100 is reserved for the power-down function (see

Table 7). These modes are software programmable by setting two

bits (DB5 and DB4) in the control register. Table 10 shows how

the state of the bits corresponds to the mode of operation of the

device. All DACs (DAC D to DAC A) can be powered down to

the selected mode by setting the corresponding four bits (DB3,

DB2, DB1, and DB0) to 1. By executing the same Command 100,

any combination of DACs is powered up by setting Bit DB5 and

Bit DB4 to normal operation mode. To select which combination

of DAC channels to power-up, set the corresponding four bits

(DB3, DB2, DB1, and DB0) to 1. See Table 11 for contents of the

input shift register during the power-down/power-up operation.

Table 10. Modes of Operation for the AD5624/AD5664

DB5

DB4

Operating Mode

0

0

Normal operation

Power-down modes

0

1

1 kΩ to GND

1

0

100 kΩ to GND

1

1

Three-state

When both bits are set to 0, the devices work normally with

their normal power consumption of 450 μA at 5 V. However, for

the three power-down modes, the supply current falls to 480 nA

at 5 V (200 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This allows

the output impedance of the device to be known while the

device is in power-down mode.

The outputs can either be connected internally to GND through

a 1 kΩ or 100 kΩ resistor, or left open circuited (three-state)

(see Figure 35).

RESISTOR

NETWORK

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

Figure 35. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and

other associated linear circuitry are shut down when power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The time to exit power-down

Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation

DB23 to

DB22

(MSB)

DB21

DB20

DB19

DB18

DB17

DB16

DB15

to DB6

DB5

DB4

DB3

DB2

DB1

DB0

(LSB)

x

1

0

0

x

x

x

x

PD1

PD0

DAC D

DAC C

DAC B

DAC A

Don’t care

Command bits (C2 to

C0)

Address bits (A2 to A0);

don’t care

Don’t

care

Power-down

mode

Power-down/power-up channel

selection, set bit to 1 to select channel