AD5624/AD5664

Data Sheet

Rev. A | Page 16 of 23

INPUT SHIFT REGISTER

The input shift register is 24 bits wide. The first two bits are don’t

care bits. The next three bits are the Command bits, C2 to C0

(see Table 7), followed by the 3-bit DAC address, A2 to A0 (see

Table 8), and then the 16-, 12-bit data-word. The data-word

comprises the 16-, 12- bit input code followed by 0 or 4 don’t

care bits for the AD5664 and AD5624 respectively (see Figure 32

and Figure 33). These data bits are transferred to the DAC

Table 7. Command Definition

C2

C1

C0

Command

0

0

0

Write to input register n

0

0

1

Update DAC register n

0

1

0

Write to input register n, update all (software

LDAC)

0

1

1

Write to and update DAC channel n

1

0

0

Power down DAC (power-up)

1

0

1

Reset

1

1

0

Load LDAC register

1

1

1

Reserved

Table 8. Address Command

A2

A1

A0

ADDRESS (n)

0

0

0

DAC A

0

0

1

DAC B

0

1

0

DAC C

0

1

1

DAC D

1

1

1

All DACs

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at least

falling edge, then this acts as an interrupt to the write sequence.

The input shift register is reset and the write sequence is seen as

invalid. Neither an update of the DAC register contents nor a

change in the operating mode occurs (see Figure 34).

POWER-ON RESET

The AD5624/AD5664 family contains a power-on reset circuit

that controls the output voltage during power-up. The AD5624/

AD5664 DAC outputs power up to 0 V and the output remains

there until a valid write sequence is made to the DAC. This is

useful in applications where it is important to know the state of

the output of the DAC while it is in the process of powering up.

X

X

C2

C1

C0

A2

A1

A0

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 32. AD5664 Input Shift Register Contents

X

X

C2

C1

C0

A2

A1

A0

XX

XX

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DB23 (MSB)

DB0 (LSB)

COMMAND BITS

ADDRESS BITS

DATA BITS

Figure 33. AD5624 Input Shift Register Contents

DIN

DB23

DB23

DB0

DB0

VALID WRITE SEQUENCE, OUTPUT UPDATES

SYNC

SCLK

INVALID WRITE SEQUENCE:

Figure 34. SYNC Interrupt Facility