uP9303

16

uP9303-DS-F0101, Aug. 2017

www.upi-semi.com

switching-regulator applications for the bulk capacitors. The

bulk capacitor’s ESR will determine the output ripple voltage

and the initial voltage drop after a high slew-rate transient.

An aluminum electrolytic capacitor’s ESR value is related

to the case size with lower ESR available in larger case

sizes.

However, the Equivalent Series Inductance (ESL) of these

capacitors increases with case size and can reduce the

usefulness of the capacitor to high slew-rate transient

loading.

Unfortunately, ESL is not a specified parameter. Work with

your capacitor supplier and measure the capacitor’s

impedance with frequency to select a suitable component.

In most cases, multiple electrolytic capacitors of small case

size perform better than a single large case capacitor.

Bootstrap Capacitor Selection

BOOT pin supplies the gate drive voltage for the upper

MOSFET. This capacitor is charged through the internal

diode when the PHASE node is low. When the upper

capacitor needs to store about 100 times the gate charge

required by the upper MOSFET. In most applications 0.1uF

to 0.47uF, X5R or X7R dielectric capacitor is adequate.

PCB Layout Considerations

High speed switching and relatively large peak currents

in a synchronous-rectified buck converter make the PCB

layout a very important part of design. Fast current

switching from one device to another in a synchronous-

rectified buck converter causes voltage spikes across the

interconnecting impedances and parasitic circuit elements.

The voltage spikes can degrade efficiency and radiate

noise that result in overvoltage stress on devices. Careful

component placement layout and printed circuit design

minimizes the voltage spikes induced in the converter.

Follow the layout guidelines for optimal performance of

uP9303

1

The upper and lower MOSFETs turn on/off and conduct

pulsed current alternatively with high slew rate transition.

Any inductance in the switched current path generates

a large voltage spike during the switching. The

interconnecting wires indicated by red heavy lines

conduct pulsed current with sharp transient and should

be part of a ground or power plane in a printed circuit

board to minimize the voltage spike. Make all the

connection the top layer with wide, copper filled areas.

2

Place the power components as physically close as

possible.

2.1 Place the input capacitors, especially the high-

frequency ceramic decoupling capacitors, directly

to the drain of upper MOSFET ad the source of the

lower MOSFET. To reduce the ESR replace the

single input capacitor with two parallel units

2.2 Place the output capacitor between the converter

and load.

3

Place the uP9303 near the upper and lower MOSFETs

with pins 1 to 4 facing the power components. Keep

the components connected to pins 4 to 8 close to the

uP9303 and away from the inductor and other noise

sources (noise sensitive components).

4

Use a dedicated grounding plane and use vias to ground

all critical components to this layer. The ground plane

layer should not have any traces and it should be as

close as possible to the layer with power MOSFETs.

Use an immediate via to connect the components to

ground plane including GND of uP9303 Use several

bigger vias for power components.

5

Apply another solid layer as a power plane and cut this

plane into smaller islands of common voltage levels.

The power plane should support the input power and

output power nodes to maintain good voltage filtering

and to keep power losses low. Also, for higher currents,

it is recommended to use a multilayer board to help

with heat sinking power components.

6

The PHASE node is subject to very high dV/dt voltages.

Stray capacitance between this island and the

surrounding circuitry tend to induce current spike and

capacitive noise coupling. Keep the sensitive circuit

away from the PHASE node and keep the PCB area

small to limit the capacitive coupling. However, the PCB

area should be kept moderate since it also acts as

main heat convection path of the lower MOSFET.

7

uP9303 sources/sinks impulse current with 2A peak to

turn on/off the upper and lower MOSFETs. The

connecting trance between the controller and gate/

source of the MOSFET should be wide and short to

minimize the parasitic inductance along the traces.

8

Flood all unused areas on all layers with copper.

Flooding with copper will reduce the temperature rise

of power component.

9

Provide local VCC decoupling between VCC and GND

to the BOOT and PHASE pins.

Application Information