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UP9303ASAC 数据表(PDF) 6 Page - uPI Group Inc. |
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UP9303ASAC 数据表(HTML) 6 Page - uPI Group Inc. |
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6 / 18 page ![]() uP9303 6 uP9303-DS-F0101, Aug. 2017 www.upi-semi.com 200kHz switching frequency. When a resistor is connected from FSET/SYN to ground, the uP9303 operates at a frequency higher than 200kHz. When a resistor is connected from FSET/SYN to VCC, the uP9303 operates at a frequency lower than 200kHz. The Figure 2 shows the relationship between switching frequency and the external resistance. R FSET to GND : ) k ( ) 200 F ( 9600 R SW FSET Ω − = R FSET to VCC : ) ( ) 200 ( 48000 Ω − = k F R SW FSET 10 100 1000 10 100 1000 RFSET to GND RFSET to VCC RFSET(kohm) Figure 2. Switching Frequency vs. FSET/SYN Resistance The switching frequency can also be synchronized to external clock from 50kHz to 500MHz applied to FSET/ SYN pin. Figure 4 depicts the clock logic of uP9303. When a resistor R FSET is connected from FSET/SYN to GND, its voltage V FSET/SYN is clamped to 2.4V. If the VFSET/STN stays between 2.0V and 3.0V for 30us, the internal clock is selected for operation (Local Clock Mode, LCM). A Schmitt trigger circuit receives the V FSET/SYN and generates a inverse squarewave that is synchronized to the V FSET/SYN when a external clock or internal clock is applied. The uP9303 works with synchronization mode if the squarewave frequency is higher than 50kHz (Remote Clock Mode RCM). The V IH and VIL of the Schmitt trigger circuit are 2/3 and 1/3 of V CC respectively. If the V FSET stays below 1/3 of 5VDD or above 2/3 of 5VDD for 30us, the uP9303 asserts clock off and turns off the converter (Clock Off Mode COM). The transitions from LCM to COM, COM to RCM or LCM to RCM are allowable. However, the transitions from COM to LCM, RCM to COM or RCM to LCM are regarded as fatal faults and not allowed. The uP9303 shuts down and latches off when forbidden mode transitions occur and can only be rest by POR of V CC. The uP9303B outputs a clock signal at CLK pin that is 180O out of phase with the operation clock. This clock can be used as synchronization for other uPI controller that features FSET/SYN pin. Output Voltage Setting The output voltage can be programmed by a resistive divider connected to the FB pin as shown in the Typical Application Circuit: 1 R 2 R 1 R V 6 . 0 V OUT + × = Overcurrent Protection (OCP) The uP9303 monitors the voltage drop across the upper MOSFET for over current protection (OCP). A resistor connected between OCSET pin and the drain of the upper MOSFET programs the OCP threshold level as shown in the Figrue 3. An internal 200uA current source flows through the R OCSET, creating a voltage VOCSET at OCSET as: OCSET IN OCSET R uA 200 V V × − = PHASE OCSET OCP comparator 200uA ROCSET VIN VOUT COCSET Figure 3. OCP Level Programming. The OCP comparator compares the V OCSET and VPHASE for over current protection when the upper MOSFET turns on. If V PHASE is lower than VOCSET, an OCP is triggered. The OCP threshold level is given by: ) ON ( DS OCSET ) ON ( DS OCSET OCSET OCP R R uA 200 R R I I × = × = Functional Description |
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