uP9303

5

uP9303-DS-F0101, Aug. 2017

www.upi-semi.com

The uP9303 is a compact synchronous-rectified buck

controller specifically designed to operate with single 12V

supply voltage and to deliver high quality output voltage. It

adopts external compensated, voltage mode control to

tightly regulate the feedback votlage to internal 0.6V

reference voltage. The switching frequency is programmable

from 50kHz to 500kHz, providing an optimal level of

integration to reduce size and cost of the power supply.

The uP9303 integrates MOSFET drivers that support

12V+12V bootstrapped voltage for high efficiency power

conversion.

The uP9303B features clock output that enables

synchronized operation of two buck converters, reducing

stress at input capacitors and EMI interference between

converters.

Other features include under voltage lockout (UVLO), under-

voltage protection, over-voltage protection and user

programmable

over-current

protection.

With

aforementioned functions, this part provides customers a

compact, high efficiency, well-protected and cost-effective

solutions. This part is available in SOP-14 package.

Supply Voltage

The uP9303 features two supply input pins: VCC and PVCC

for control circuit and gate drivers respectively. In real

application, connect VCC and PVCC to a well-decoupled

10.8V to 13.2V supply voltage as shown in the Typical

Application Circuit. A minimum 1uF ceramic capacitor

physically near the supply input pins are required for locally

bypassing the supply voltages.

An internal linear regulator regulates VCC supply voltage

into a 5.0V voltage 5VDD for internal control logic circuit.

No external bypass capacitor is required for filtering the

5VDD voltage.

The uP9303 integrates MOSFET gate drives that are

powered from the PVCC pin and support 12V+12V driving

capability. Converters that consist of uP9303 feature high

efficiency without special consideration on the selection

of MOSFETs.

Power On Reset and Chip Enable

The uP9303 continuously monitors 1.) VCC pin voltage,

2.) EN pin voltage, 3.) OCSET pin voltage and 4.) FSET/

SYN pin voltage for power on reset. The uP9303 is enabled

only when all the POR is released. The POR threshold

voltage are 9.5V, 1.3V, 1.3V and 0.4V at VCC, EN, OCSET,

and FSET/SYN rising respectively. Before POR is released,

the uP9303 is disabled, SS pin is pulled low to ground and

both gate drivers are turned off.

Because the PVCC voltage is not monitored by POR

circuitry, it must be connected to VCC pin externally to

ensure PVCC is ready when POR is released.

Soft Start

A capacitor C

behavior of output voltage as shown in Figure 1.

Before POR is released, the SS pin is internally pulled

low to ground. When POR is released, an internal 30uA

current source starts to charge C

ramping-up voltage V

T

C

uA

30

V

SS

SS

×

=

Time

Voltage

4.2V

1.8V

0.6V

T0

T1

T2

Figure 1. Softstart Behavior.

The error amplifier is a three-input device (referring to the

Functional Block Diagram). Reference voltage V

soft start voltage V

the behavior of the non-inverting input of the error amplifier.

The SSE voltage is clamped as:

4

V

8

.

1

C

/

T

uA

30

4

V

8

.

1

V

V

SS

SS

SSE

−

×

=

−

=

Consequently, when V

voltage V

and 4.2V, the feedback voltage V

0V to 0.6V. When V

0.6V reference takes over the control of error amplifier

and the feedback voltage is regulated to V

time, the uP9303 asserts soft start end and enables the

under voltage protection.

The output voltage ramp-up time can be calculated as:

uA

30

C

V

4

.

2

I

C

)

V

8

.

1

V

2

.

4

(

1

T

2

T

T

SS

SS

SS

SS

×

=

×

−

=

−

=

Switching Frequency Setting

The uP9303 features adjustable switching frequency by a

resistor connected to the FSET/SYN pin. When the FSET/

SYN pin is floating, the uP9303 operates at a free-running

Functional Description