uP9303

7

uP9303-DS-F0101, Aug. 2017

www.upi-semi.com

An OCP will shut down the device and discharge the C

SS

with a 30uA sinking current source. When the C

discharged completely, another soft start cycle is initiated.

If the over current condition is not removed during the

soft start cycle, the uP9303 will shut down immediately

when another OCP is triggered. However, the V

rising to 4V to complete the soft start cycle before the

internal 30uA current source discharges the C

current conditon is not removed, the re-soft-start cycle will

repeat 3 times and then latch off uP9303.

To avoid false trigger of OCP, variations of all parameters

in above equation should be well considered, including:

1.) The R

the gate to source voltage. Consider the highest operation

temperature and lowest gate to source voltage.

2.) Consider the minimum I

R

3.) Consider the inductor ripple current.

Functional Description

2.4V

Current

Limited

Local Clock

Generator

Clock Logic

Clock Logic

Remote Clock (RC): RC Frequency > 50kHz

Clock Off: Otherwise

Ramp

Generator

Sampled and

Held Current

Ramp

FSET/SYN

CLK

To turn off the current

source when RC = 1

for local

clock

for remote

clock

Under Voltage Protection (UVP)

The FB voltage is monitored for undervoltage protection

after soft start end is asserted. If the FB voltage is lower

than 0.3V (50% of 0.6V reference voltage), the UVP is

triggered and shuts down the uP9303 with about 10us time

delay. The uP9303 turns off both upper and lower

MOSFETs when UVP is triggered. The UVP is a latch-off

type protection and can only be reset by POR of the device.

Over Voltage Protection (OVP)

The FB voltage is monitored for overvoltage protection.

If the FB voltage is higher than 0.78V (130% of 0.6V

reference voltage), the OVP is triggered and shuts down

the uP9303 with about 10us time delay. The uP9303 turns

off the upper and lower MOSFET when OVP is triggered.

The OVP is a latch-off type protection and can only be

reset by POR of the device.

Figure 4. Clock Logic of uP9303