M36LLR8760DF datasheet(8/19 Pages) STMICROELECTRONICS

8 / 19 page

M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1

8/19

a negative transition of Chip Enable or Latch En-

able is required to ensure valid data outputs.

The Reset pin can be interfaced with 3V logic with-

out any additional circuitry. It can be tied to VRPH

(refer to Table 8., Flash 1 and Flash 2 DC Charac-

teristics - Voltages).

PSRAM Chip Enable input (EP). The Chip En-

able input activates the PSRAM when driven Low

(asserted). When deasserted (VIH), the device is

disabled, and goes automatically in low-power

Standby mode or Deep Power-down mode.

PSRAM Write Enable (WP). Write Enable, WP,

controls the Bus Write operation of the PSRAM.

When asserted (VIL), the device is in Write mode

and Write operations can be performed either to

the configuration registers or to the memory array.

PSRAM Output Enable (GP). Output

Enable,

GP, provides a high speed tri-state control, allow-

ing fast read/write cycles to be achieved with the

common I/O data bus.

PSRAM Upper Byte Enable (UBP). The

Upper

Byte En-able, UBP, gates the data on the Upper

Byte Data Inputs/Outputs (DQ8-DQ15) to or from

the upper part of the selected address during a

Write or Read operation.

PSRAM Lower Byte Enable (LBP). The

Lower

Byte Enable, LBP, gates the data on the Lower

Byte Data Inputs/Outputs (DQ0-DQ7) to or from

the lower part of the selected address during a

Write or Read operation.

If both LBP and UBP are disabled (High) during an

operation, the device will disable the data bus from

receiving or transmitting data. Although the device

will seem to be deselected, it remains in an active

mode as long as EP remains Low.

PSRAM Configuration Register Enable (CRP).

When this signal is driven High, VIH, Write opera-

tions load either the value of the Refresh Configu-

ration Register (RCR) or the Bus configuration

VDDF1/VDDF2 Supply Voltages. VDDF1

and

VDDF2 provide the power supply to the internal

cores of Flash 1 and Flash 2, respectively. It is the

main power supply for all Flash memory opera-

tions (Read, Program and Erase).

VCCP Supply Voltage. VCCP provides the power

supply to the internal core of the PSRAM device. It

is the main power supply for all PSRAM opera-

tions.

VDDQF Supply Voltage. VDDQF

provides

the

power supply for the Flash memory. This allows all

Outputs to be powered independently of the Flash

memory and SRAM core power supplies, VDDF

and VCCP.

VPPF Program Supply Voltage. VPPF is both a

control input and a power supply pin for the Flash

memories. The two functions are selected by the

voltage range applied to the pin.

If VPPF is kept in a low voltage range (0V to VDDQF)

VPPF is seen as a control input. In this case a volt-

age lower than VPPLK gives an absolute protection

against Program or Erase, while VPPF > VPP1 en-

ables these functions (see Tables 6 and 8, DC

Characteristics for the relevant values). VPPF is

only sampled at the beginning of a Program or

Erase; a change in its value after the operation has

started does not have any effect and Program or

Erase operations continue.

If VPPF is in the range of VPPH it acts as a power

supply pin. In this condition VPPF must be stable

until the Program/Erase algorithm is completed.

VSS Ground. VSS is the common ground refer-

ence for all voltage measurements in the Flash

(core and I/O Buffers) and PSRAM chips. It must

be connected to the system ground.

Note: Each Flash memory device in a system

should have their supply voltage (VDDF) and

the program supply voltage VPPF decoupled

with a 0.1µF ceramic capacitor close to the pin

(high frequency, inherently low inductance ca-

pacitors should be as close as possible to the

package). See Figure 6., AC Measurement

Load Circuit. The PCB track widths should be

sufficient to carry the required VPPF program

and erase currents.

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