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M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1

PART NUMBERING

Table 11. Ordering Information Scheme

Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available op-

tions (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST-

Microelectronics Sales Office nearest to you.

Example:

M36 L

L

R 8

7 6

0

T 1 ZAQ T

Device Type

M36 = Multi-Chip Package (Multiple Flash + RAM)

Flash 1 Architecture

L = Multi-Level, Multiple Bank, Burst mode

Flash 2 Architecture

L = Multi-Level, Multiple Bank, Burst mode

Operating Voltage

Flash 1 Density

8 = 256 Mbits

Flash 2 Density

7 = 128 Mbits

RAM 1 Density

6 = 64 Mbits

RAM 0 Density

0 = No Die

Parameter Blocks Location

T = Top Boot Block Flash

B = Bottom Boot Block Flash

D = Mixed (Flash 1 Bottom, Flash 2 Top)

M = Mixed (Flash 1 Top, Flash 2 Bottom)

Product Version

1 = 0.13µm Flash technology (2 Chip Enable inputs, one for each Flash memory), 85ns speed;

0.11µm PSRAM, 70ns speed, burst mode

Package

ZAQ = Stacked LFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch

Option

Blank = Standard Packing

T = Tape & Reel Packing

E = Lead-free and RoHS Standard packing

F = Lead-free and RoHS Tape & Reel packing