HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

9

December 28, 2004

Indirect Addressing Register

Location 00H is an indirect addressing register that is

not physically implemented. Any read/write operation of

[00H] accesses data memory pointed to by MP (01H).

Reading location 00H itself indirectly will return the re-

sult 00H. Writing indirectly results in no operation.

The memory pointer register MP (01H) is a 7-bit register.

The bit 7 of MP is undefined and reading will return the

result

²1². Any writing operation to MP will only transfer the

lower 7-bit data to MP.

Accumulator

The accumulator is closely related to ALU operations. It

is also mapped to location 05H of the data memory and

can carry out immediate data operations. The data

movement between two data memory locations must

pass through the accumulator.

Arithmetic and Logic Unit

- ALU

This circuit performs 8-bit arithmetic and logic opera-

tions. The ALU provides the following functions:

The ALU not only saves the results of a data operation but

also changes the status register.

Status Register

- STATUS

This 8-bit register (0AH) contains the zero flag (Z), carry

flag (C), auxiliary carry flag (AC), overflow flag (OV),

power down flag (PDF), and watchdog time-out flag

(TO). It also records the status information and controls

the operation sequence.

Bit No.

Label

Function

0C

C is set if an operation results in a carry during an addition operation or if a borrow does not take

place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate

through carry instruction.

1AC

AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the

high nibble into the low nibble in subtraction, otherwise AC is cleared.

2

Z

Z is set if the result of an arithmetic or logic operation is zero, otherwise Z is cleared.

3OV

OV is set if an operation results in a carry into the highest-order bit but not a carry out of the high-

est-order bit, or vice versa, otherwise OV is cleared.

4

PDF

PDF is cleared by a system power-up or executing the

²CLR WDT² instruction. PDF is set by exe-

cuting the

²HALT² instruction.

5TO

TO is cleared by a system power-up or executing the

²CLR WDT² or ²HALT² instruction. TO is

set by a WDT time-out.

6, 7

¾

Unused bit, read as

²0²

Status (0AH) Register

S p e c i a l P u r p o s e

D A T A M E M O R Y

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

I n d i r e c t A d d r e s s i n g R e g i s t e r

M P

A C C

P C L

T B L P

T B L H

S T A T U S

I N T C

T M R

T M R C

P A

P A C

P B

P B C

P D

P D C

P W M

A D R L

A D R H

A D C R

A C S R

: U n u s e d

R e a d a s " 0 0 "

3 F H

2 4 H

2 0 H

2 1 H

2 2 H

2 3 H

G e n e r a l P u r p o s e

D A T A M E M O R Y

( 6 4 B y t e s )

7 F H

4 0 H

RAM Mapping for the HT46R47/HT46C47