HT46R46 datasheet(11/42 Pages) HOLTEK

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HT46R46/HT46C46/HT46R47/HT46C47

Rev. 1.00

December 28, 2004

Interrupt Source

Priority

Vector

External Interrupt

04H

Timer/Event Counter Overflow

08H

A/D Converter Interrupt

0CH

The timer/event counter interrupt request flag (TF), ex-

ternal interrupt request flag (EIF), A/D converter request

flag (ADF), enable timer/event counter bit (ETI), enable

external interrupt bit (EEI), enable A/D converter inter-

rupt bit (EADI) and enable master interrupt bit (EMI)

constitute an interrupt control register (INTC) which is

located at 0BH in the data memory. EMI, EEI, ETI, EADI

are used to control the enabling/disabling of interrupts.

These bits prevent the requested interrupt from being

serviced. Once the interrupt request flags (TF, EIF, ADF)

are set, they will remain in the INTC register until the in-

terrupts are serviced or cleared by a software instruc-

tion.

It is recommended that a program does not use the

CALL subroutine within the interrupt subroutine. In-

terrupts often occur in an unpredictable manner or

need to be serviced immediately in some applications.

If only one stack is left and enabling the interrupt is not

well controlled, the original control sequence will be dam-

aged once the

²CALL² operates in the interrupt subrou-

tine.

Oscillator Configuration

There are two oscillator circuits in the microcontroller.

Both are designed for system clocks, namely the RC os-

cillator and the Crystal oscillator, which are determined

by the options. No matter what oscillator type is se-

lected, the signal provides the system clock. The HALT

mode stops the system oscillator and ignores an exter-

nal signal to conserve power.

If an RC oscillator is used, an external resistor between

OSC1 and VSS is required and the resistance must

range from 30k

W to 750kW. The system clock, divided

by 4, is available on OSC2, which can be used to syn-

chronize external logic. The RC oscillator provides the

most cost effective solution. However, the frequency of

oscillation may vary with VDD, temperatures and the

chip itself due to process variations. It is, therefore, not

suitable for timing sensitive operations where an accu-

rate oscillator frequency is desired.

If the Crystal oscillator is used, a crystal across OSC1

and OSC2 is needed to provide the feedback and phase

shift required for the oscillator, and no other external

components are required. Instead of a crystal, a resona-

tor can also be connected between OSC1 and OSC2 to

get a frequency reference, but two external capacitors in

OSC1 and OSC2 are required (If the oscillating fre-

quency is less than 1MHz).

The WDT oscillator is a free running on-chip RC oscilla-

tor, and no external components are required. Even if

the system enters the power down mode, the system

clock is stopped, but the WDT oscillator still works with a

period of approximately 65

ms@5V. The WDT oscillator

can be disabled by options to conserve power.

Watchdog Timer

- WDT

The clock source of WDT is implemented by a dedicated

RC oscillator (WDT oscillator) or instruction clock (sys-

tem clock divided by 4), decided by options. This timer is

designed to prevent a software malfunction or sequence

from jumping to an unknown location with unpredictable

results. The Watchdog Timer can be disabled by an op-

tion. If the Watchdog Timer is disabled, all the execu-

tions related to the WDT result in no operation.

Once the internal oscillator (RC oscillator with a period

of 65

ms@5V normally) is selected, it is divided by

32768~65536 to get the time-out period of approxi-

mately 2.1s~4.3s. This time-out period may vary with

temperatures, VDD and process variations. If the WDT

oscillator is disabled, the WDT clock may still come from

the instruction clock and operate in the same manner

except that in the HALT state the WDT may stop count-

ing and lose its protecting purpose. In this situation the

logic can only be restarted by external logic.

If the device operates in a noisy environment, using the

on-chip RC oscillator (WDT OSC) is strongly recom-

mended, since the HALT will stop the system clock.

The WDT overflow under normal operation will initialize

²chip reset² and set the status bit ²TO². But in the HALT

mode, the overflow will initialize a

²warm reset², and

only the program counter and SP are reset to zero. To

clear the contents of WDT, three methods are adopted;

external reset (a low level to RES), software instruction

and a HALT instruction. The software instruction include

²CLR WDT² and the other set -²CLR WDT1² and ²CLR

WDT2

². Of these two types of instruction, only one can

be active depending on the options

-²CLR WDT times

selection option

².Ifthe ²CLR WDT² is selected (i.e. CLR

WDT times equal one), any execution of the

²CLR

WDT

² instruction will clear the WDT. In the case that

²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLR

WDT times equal two), these two instructions must be

executed to clear the WDT; otherwise, the WDT may re-

set the chip as a result of time-out.

C r y s t a l O s c i l l a t o r

R C O s c i l l a t o r

O S C 1

O S C 2

N M O S O p e n D r a i n

O S C 2

f S Y S / 4

O S C 1

V D D

System Oscillator

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